поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

DP8430V датащи(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали DP8430V
подробное описание детали  microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
PDF  56 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8430V датащи(HTML) 9 Page - National Semiconductor (TI)

Back Button DP8430V Datasheet HTML 5Page - National Semiconductor (TI) DP8430V Datasheet HTML 6Page - National Semiconductor (TI) DP8430V Datasheet HTML 7Page - National Semiconductor (TI) DP8430V Datasheet HTML 8Page - National Semiconductor (TI) DP8430V Datasheet HTML 9Page - National Semiconductor (TI) DP8430V Datasheet HTML 10Page - National Semiconductor (TI) DP8430V Datasheet HTML 11Page - National Semiconductor (TI) DP8430V Datasheet HTML 12Page - National Semiconductor (TI) DP8430V Datasheet HTML 13Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 56 page
background image
30 Programming and Resetting (Continued)
33 PROGRAMMING BIT DEFINITIONS
Symbol
Description
ECAS0
Extend CAS Refresh Request Select
0
The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB DP8432V only) is negated
The WE output pin will function as write enable Automatic Internal Refresh selected
1
The CASn outputs will be negated during an acccess (Port A (or Port B DP8432V only)) when their
corresponding ECASn inputs are negated This feature allows the CAS outputs to be extended beyond the RAS
outputs negating Scrubbing refreshes are NOT affected During scrubbing refreshes the CAS outputs will negate
along with the RAS outputs regardless of the state of the ECAS inputs
Externally Controlled Refresh selected WE will function as ReFresh ReQuest (RFRQ)
B1
Access Mode Select
0
ACCESS MODE 0
ALE pulsing high sets an internal latch On the next positive edge of CLK the access (RAS)
will start AREQ will terminate the access
1
ACCESS MODE 1
ADS asserted starts the access (RAS) immediately AREQ will terminate the access
B0
Address Latch Mode
0
ADS or ALE asserted for Port A or AREQB asserted for Port B with the appropriate GRANT latch the input row
column and bank address
1
The row column and bank latches are fall through
C9
Delay CAS during WRITE Accesses
0
CAS is treated the same for both READ and WRITE accesses
1
During WRITE accesses CAS will be asserted by the event that occurs last CAS asserted by the internal delay
line or CAS asserted on the positive edge of CLK after RAS is asserted
C8
Row Address Hold Time
0
Row Address Hold Time e 25 ns minimum
1
Row Address Hold Time e 15 ns minimum
C7
Column Address Setup Time
0
Column Address Setup Time e 10 ns miniumum
1
Column Address Setup Time e 0 ns minimum
C6 C5 C4
RAS and CAS Configuration ModesError Scrubbing during Refresh
0 0 0
RAS0 – 3 and CAS0 – 3 are all selected during an access ECASn must be asserted for CASn to be asserted
B0 and B1 are not used during an access Error scrubbing during refresh
0 0 1
RAS and CAS pairs are selected during an access by B1 ECASn must be asserted for CASn to be asserted
B1 e 0 during an access selects RAS0 – 1 and CAS0–1
B1 e 1 during an access selects RAS2 – 3 and CAS2–3
B0 is not used during an Access
Error scrubbing during refresh
0 1 0
RAS and CAS singles are selected during an access by B0 – 1 ECASn must be asserted for CASn to be asserted
B1 e 0 B0 e 0 during an access selects RAS0 and CAS0
B1 e 0 B0 e 1 during an access selects RAS1 and CAS1
B1 e 1 B0 e 0 during an access selects RAS2 and CAS2
B1 e 1 B0 e 1 during an access selects RAS3 and CAS3
Error scrubbing during refresh
0 1 1
RAS0 – 3 and CAS0 – 3 are all selected during an access ECASn must be asserted for CASn to be asserted
B1 B0 are not used during an access
No error scrubbing (RAS only refreshing)
1 0 0
RAS pairs are selected by B1 CAS0 – 3 are all selected ECASn must be asserted for CASn to be asserted
B1 e 0 during an access selects RAS0 – 1 and CAS0–3
B1 e 1 during an access selects RAS2 – 3 and CAS0–3
B0 is not used during an access
No error scrubbing
9



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com