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DP8430V датащи(PDF) 52 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали DP8430V
подробное описание детали  microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
PDF  56 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8430V датащи(HTML) 52 Page - National Semiconductor (TI)

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130 AC Timing Parameters (Continued)
Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs
per bank including trace capacitance (Note 2)
Two different loads are specified
CL e 50 pF loads on all outputs except
CL e 150 pF loads on Q0–8 9 10 and WE or
CH e 50 pF loads on all outputs except
CH e 125 pF loads on RAS0–3 and CAS0–3 and
CH e 380 pF loads on Q0–8 9 10 and WE
Mode 1 Dual Access
DP8430V31V32V-33
Number
Symbol
Parameter Description
CL
CH
Min
Max
Min
Max
450
tSADDCKG
Row Address Setup to CLK High That
Asserts RAS following a GRANTB
10
12
Port Change to Ensure tASR e 0ns
451
tPCKRASG
CLK High to RAS Asserted
30
34
for Pending Access
452
tPCLKDL2
CLK to DTACK Asserted for Delayed
37
37
Accesses (Programmed as DTACK0)
453a
tPCKCASG0
CLK High to CAS Asserted
for Pending Access
81
88
(tRAH e 15 ns tASC e 0 ns)
453b
tPCKCASG1
CLK High to CAS Asserted
for Pending Access
91
98
(tRAH e 15 ns tASC e 10 ns)
453c
tPCKCASG2
CLK High to CAS Asserted
for Pending Access
91
98
(tRAH e 25 ns tASC e 0 ns)
453d
tPCKCASG3
CLK High to CAS Asserted
for Pending Access
101
108
(tRAH e 25 ns tASC e 10 ns)
454
tSBADDCKG
Bank Address Valid Setup to CLK High
33
that Asserts RAS for Pending Access
455
tSADSCK0
ADS Asserted Setup to CLK High
8
8
52



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