DP8430V datasheet(7/56 Pages) NSC

7 / 56 page

20 Signal Descriptions (Continued)

Device (If not

Input

Description

Name

Applicable to All)

Output

26 COMMON DUAL PORT SIGNALS

GRANTB

DP8432V

GRANT B

This output indicates which port is currently granted access to the DRAM

array When GRANTB is asserted Port B has access to the array When GRANTB is

only

negated Port A has access to the DRAM array This signal is used to multiplex the

signals R0 – 8 9 10 C0 – 8 9 10 B0 – 1 WIN LOCK and ECAS0 – 3 to the DP8432V

when using dual accessing

LOCK

DP8432V

LOCK

This input can be used by the currently granted port to ‘‘lock out’’ the other

port from the DRAM array by inserting wait states into the locked out port’s access

only

cycle until LOCK is negated

27 POWER SIGNALS AND CAPACITOR INPUT

VCC

POWER

Supply Voltage

GND

GROUND

Supply Voltage Reference

CAP

CAPACITOR

This input is used by the internal PLL for stabilization The value of the

ceramic capacitor should be 01 mF and should be connected between this input and

ground

28 CLOCK INPUTS

There are two clock inputs to the DP8430V31V32V CLK and DELCLK These two clocks may both be tied to the same clock

input or they may be two separate clocks running at different frequencies asynchronous to each other

CLK

SYSTEM CLOCK

This input may be in the range of 0 Hz up to 25 MHz This input is

generally a constant frequency but it may be controlled externally to change

frequencies or perhaps be stopped for some arbitrary period of time

This input provides the clock to the internal state machine that arbitrates between

accesses and refreshes This clock’s positive edges and negative levels are used to

extend the WAIT (DTACK) signals Ths clock is also used as the reference for the

RAS precharge time and RAS low time during refresh

All Port A and Port B accesses are assumed to be synchronous to the system clock

CLK

DELCLK

DELAY LINE CLOCK

The input frequency to DELCLK should be in the range of

12 MHz to 40 MHz This frequency will be internally divided by choosing a divisor

when programming the part The result of the division should be a frequency of

2 MHz This is because the Phase Lock Loop that generates the delay line assumes

an input clock frequency of 2 MHz If after dividing DELCLK by one of the internal

divisors (6 8 10 12 14 16 18 or 20) the resulting frequency is not 2 MHz the delay

line will suffer

For example if the DELCLK frequency is 18 MHz and a divide by 8 is chosen

programming bits C0 – 2 the resulting frequency will be 225 which is 125% off of

2 MHz Therefore the DP8430V31V32V will produce delays that are shorter (faster

delays) than what is intended On the other hand if divide by 10 was chosen the

resulting frequency will be 18 MHz this frequency will produce delays that are longer

(slower delays) than intended

This clock is also divided to create the internal refresh clock

DP8430V датащи(PDF) 7 Page - National Semiconductor (TI)

DP8430V датащи(HTML) 7 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

датащи скачать

ссылки URL