DP8430V datasheet(3/56 Pages) NSC

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10 Introduction

The DP8430V31V32V DRAM controllers are the latest

devices based upon the DP8420A21A22A predecessors

The DP8430V31V32V implement changes which do not

allow them to be pin compatible with any of the DP842XA or

the DP842XV DRAM controllers Two changes have been

made The limits for the input frequency to DELCLK have

been increased making possible the use of a single clock

source A RESET input is now available making the reset

procedure easier These changes although minimal facili-

tate the use of the controllers and make them even more

attractive for high performance applications The controllers

incorporate address latches refresh counter rowcolumn

refresh address multiplexer delay line refreshaccesspre-

charge arbitration logic and high capacitive drivers The

DP8430V31V32V DRAM controllers allow any manufac-

turer’s CPU or bus to directly interface to DRAM arrays up to

64 Mbytes in size

Reset

The user must reset the controller before programming it

Reset is achieved by asserting the RESET input for at least

16 positive edges of clock

Programming

After reset the user can program the controller by either

one of two methods Mode Load Only Programming or Chip

Select Access Programming

The chip is programmed

through the address bus

Initialization Period

Once the DP8430V31V32V has been programmed for the

first time a 60 ms initialization period is entered During this

time the DRC performs refreshes to the DRAM array so

further warm up cycles are unnecessary The initialization

period is entered only after the first programming after a

reset

Accessing Modes

After resetting and programming the chip the DP8430V

31V32V is ready to access the DRAM There are two

modes of accessing with these controllers Mode 0 which

indicates RAS synchronously and Mode 1 which indicates

RAS asynchronously

Refresh Modes

Two refresh modes can be programmed The user can

choose Automatic Internal Refresh or Externally Controlled

Refresh With any refresh mode the user can perform burst

refreshes

Refresh Types

There are three types of refreshing available Conventional

Staggered and Error Scrubbing Any refresh control mode

can be used with any type of refresh

Wait Support

The DP8430V31V32V have wait support available as

DTACK or WAIT Both are programmable DTACK Data

Transfer ACKnowledge is useful for processors whose wait

signal is active high WAIT is useful for those processors

whose wait signal is active low The user can choose either

at programming These signals are used by the on chip arbi-

ter to insert wait states to guarantee the arbitration between

accesses refreshes and precharge Both signals are inde-

pendent of the access mode chosen and both signals can

be dynamically delayed further through the WAITIN signal to

the DP8430V31V32V

Sequential Accesses (Static ColumnPage Mode)

The DP8430V31V32V have address latches used to

latch the bank row and column address inputs Once the

address is latched a COLumn INCrement (COLINC) feature

can be used to increment the column address The address

latches can also be programmed to be fall through COLINC

can be used for Sequential Accesses of Static Column

DRAMs Also COLINC in conjunction with ECAS inputs can

be used for Sequential Accesses to Page Mode DRAMs

RAS and CAS Configuration (Byte Writing)

The RAS and CAS drivers can be configured to drive a one

two or four bank memory array up to 32 bits in width The

ECAS signals can then be used to select one of four CAS

drivers for Byte Writing with no extra logic

Memory Interleaving

When configuring the DP8430V31V32V for more than

one bank Memory Interleaving can be used By tying the

low order address bits to the bank select lines B0 and B1

sequential back to back accesses will not be delayed since

these controllers have separate precharge counters per

bank

Address Pipelining

The DP8430V31V32V are capable of performing Address

Pipelining In address pipelining the DRC will guarantee the

column address hold time and switch the internal multiple-

xor to place the row address on the address bus At this

time another memory access to another bank can be initiat-

Dual Accessing

Finally the DP8432V has all the features previously men-

tioned and unlike the DP8430V31V the DP8432V has a

second port to allow a second CPU to access the same

memory array The DP8432V has four signals to support

Dual Accessing these signals are AREQB ATACKB LOCK

and GRANTB All arbitration for the two ports and refresh is

done on chip by the controller through the insertion of wait

states Since the DP8432V has only one input address bus

the address lines must be multiplexed externally The signal

GRANTB can be used for this purpose

Terminology

The following explains the terminology used in this data

sheet The terms negated and asserted are used Asserted

refers to a ‘‘true’’ signal Thus ‘‘ECAS0 asserted’’ means

the ECAS0 input is at a logic 0 The term ‘‘COLINC assert-

ed’’ means the COLINC input is at a logic 1 The term negat-

ed refers to a ‘‘false’’ signal Thus ‘‘ECAS0 negated’’

means the ECAS0 input is at a logic 1 The term ‘‘COLINC

negated’’ means the input COLINC is at a logic 0 The table

shown below clarifies this terminology

Signal

Action

Logic Level

Active High

Asserted

High

Active High

Negated

Low

Active Low

Asserted

Low

Active Low

Negated

High

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