DP8430V datasheet(8/56 Pages) NSC

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30 Programming and Resetting

The DP8430V31V32V must be reset before it can be pro-

grammed After reset the DRAM controller is programmed

through the address bus by either one of two methods

Mode Load Only Programming or Chip Select Access Pro-

gramming After the first programming after a reset the chip

enters a 60 ms initialization period During this period the

controller performs refreshes every 13 msor15 ms this

makes further DRAM warm up cycles unnecessary After

this stage the DRAM controller can be programmed as

many times as the user wishes and the 60 ms initialization

period will not be entered into unless the chip is reset and

programmed again During the 60 ms initialization period

RFIP is asserted and RAS toggles every 13 msor15 ms

depending on the programming bit for refresh (C3) CAS will

be negated and the Q outputs will count from 0 to 2047

refreshing the entire DRAM array The initialization time pe-

riod is given by the following formula T e 4096

(Clock

Divisor Select)

(Refresh Clock Fine Tune)(DELCLK Frq)

31 RESET

The DP8430V31V32V have a RESET input pin which fa-

cilitates the reset procedure required for proper operation

Reset is accomplished by asserting the RESET input for at

least 16 positive edges of clock as shown in

Figure 5

The DRC may be programmed anytime on the fly but the

user must make sure that no access or refresh is in prog-

ress RESET is asynchronous

32 PROGRAMMING METHODS

321 Mode Load Only Programming

To use this method the user asserts ML enabling the inter-

nal programming register After ML is asserted a valid pro-

gramming selection is placed on the address bus B0 B1

and ECAS0 inputs then ML is negated When ML is negat-

ed the programming bits are latched into the internal pro-

gramming register and the DP8430V31V32V is pro-

grammed see

Figure 6 When programming the chip the

controller must not be refreshing RFIP must be high (1) to

have a successful programming

322 Chip Selected Access Programming

The chip can also be programmed by performing a chip

selected access To program the chip using this method

ML is asserted then CS is asserted and a valid program-

ming selection is placed on the address bus When AREQ is

asserted the programming bits affecting the wait logic be-

come effective immediately then DTACK is asserted allow-

ing the access to terminate After the access ML is negated

and the rest of the programming bits take effect

TLF11118 – 5

FIGURE 5 Reset

TLF11118 – 6

FIGURE 6 ML Only Programming

TLF11118 – 7

FIGURE 7 CS Access Programming

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