MEC1322 datasheet(267/456 Pages) MICROCHIP

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DS00001719D-page 267

MEC1322

21.9.6

DMA CHANNEL N DEVICE ADDRESS

21.9.7

DMA CHANNEL N CONTROL

Offset

0Ch

Bits

Description

Type

Default

Reset

Event

31:0 DEVICE_ADDRESS

This is the Master Device address.

This is used as the address that will access the Device on the DMA.

The Device is defined as the Master of the DMA transfer; as in the

device that is controlling the Hardware Flow Control.

This field is updated by Hardware after every Data Packet transfer

by the size of the transfer, as defined by DMA Channel Con-

trol:Transfer Size while the DMA Channel Control:Increment Device

Address is Enabled.

Note:

This field is only as large as the maximum allowed AHB

Address Size in the system. If the HADDR size is 24 Bits,

then Bits [31:24] will be RESERVED.

R/W

0000h

RESET

Offset

10h

Bits

Description

Type

Default

Reset

Event

31:26 Reserved

25 TRANSFER_ABORT

This is used to abort the current transfer on this DMA Channel. The

aborted transfer will be forced to terminate immediately.

R/W

RESET

24 TRANSFER_GO

This is used for the Firmware Flow Control DMA transfer.

This is used to start a transfer under the Firmware Flow Control.

Do not use this in conjunction with the Hardware Flow Control;

DMA Channel Control:Disable Hardware Flow Control

must be

set in order for this field to function correctly.

R/W

RESET

23 Reserved

22:20 TRANSFER_SIZE

This is the transfer size in Bytes of each Data Packet transfer.

Note:

The transfer size must be a legal transfer size. Valid

sizes are 1, 2 and 4 Bytes.

R/W

RESET

19 DISABLE_HARDWARE_FLOW_CONTROL

This will Disable the Hardware Flow Control. When disabled, any

DMA Master device attempting to communicate to the DMA over the

DMA Flow Control Interface (Ports: dma_req, dma_term, and

dma_done)

will be ignored.

This should be set before using the DMA channel in Firmware Flow

Control

mode.

RESET

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