MEC1322 datasheet(54/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 54

 2014 - 2015 Microchip Technology Inc.

Note 1: The minimum low pulse provided to initiate reset = 20ns.

2: There is no glitch protection or noise filtering (i.e. a vary narrow noise pulse cause a reset).

3.7

Chip Power Management Features

This device is designed to always operate in its lowest power state during normal operation. In addition, this device

offers additional programmable options to put individual logical blocks to sleep as defined in Section 3.7.1, "Block Low

Power Modes," on page 54.

3.7.1

BLOCK LOW POWER MODES

All power related control signals are generated and monitored centrally in the chip’s Power, Clocks, and Resets (PCR)

block. The power manager of the PCR block uses a sleep interface to communicate with all the blocks. The sleep inter-

face consists of three signals:

• sleep_en (request to sleep the block) is generated by the PCR block. A group of sleep_en signals are gener-

ated for every clock segment. Each group consists of a sleep_en signal for every block in that clock segment.

• clk_req (request clock on) is generated by every block. They are grouped by blocks on the same clock segment.

The PCR monitors these signals to see when it can gate off clocks.

• reset_en (reset on sleep) bits determine if the block (including registers) will be reset when it enters sleep mode.

A block can always drive clk_req low synchronously, but it MUST drive it high asynchronously since its internal clocks

are gated and it has to assume that the clock input itself is gated. Therefore the block can only drive clk_req high as a

result of a register access or some other input signal.

The following table defines a block’s power management protocol:

A wake event clears all sleep enable bits momentarily, and then returns the sleep enable bits back to their original state.

The block that needs to respond to the wake event will do so. See Section 15.8.1, "WAKE Generation," on page 194.

The Sleep Enable, Clock Required and Reset Enable registers are defined in Section 3.8, "EC-Only Registers," on

page 55.

Power State

sleep_en

clk_req

Description

Normal operation

Low

Block is idle and NOT requesting clocks. The block gates its

own internal clock.

Normal operation

Low

High

Block is NOT idle and requests clocks.

Request sleep

Rising Edge

Low

Block is IDLE and enters sleep mode immediately. The block

gates its own internal clock. The block cannot request clocks

again until sleep_en goes low.

Request sleep

Rising Edge High then

Low

Block is not IDLE and will stop requesting clocks and enter

sleep when it finishes what it is doing. This delay is block

specific, but should be less than 1 ms. The block gates its

own internal clock. After driving clk_req low, the block cannot

request clocks again until sleep_en goes low.

High

sleep_en. Therefore the block ungates its internal clock and

drives clk_req high during the access. The block will regate

its internal clock and drive clk_req low when the access is

done.

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