 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
MEC1322 датащи(PDF) 96 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MEC1322 датащи(HTML) 96 Page - Microchip Technology |
|
|
96 / 456 page  MEC1322 DS00001719D-page 96 2014 - 2015 Microchip Technology Inc. 5.11.3 EC SERIRQ REGISTER 5.11.4 EC CLOCK CONTROL REGISTER 4CONFIG_ERR This bit is set to 1 whenever EN_INTERNAL_ERR is 1 and an LPC Configuration access causes an internal bus error. Once set, it remains set until cleared by being written with a 1. R/WC 0h VCC1_R ESET 3 RUNTIME_ERR This bit is set to 1 whenever EN_INTERNAL_ERR is 1 and an LPC I/O access causes an internal bus error. This error will only occur if a BAR is misconfigured. Once set, it remains set until cleared by being written with a 1. R/WC 0h VCC1_R ESET 2 BAR_CONFLICT This bit is set to 1 whenever a BAR conflict occurs on an LPC address. A Bar conflict occurs when more than one BAR matches the address during of an LPC cycle access. Once this bit is set, it remains set until cleared by being written with a 1. R/WC 0h VCC1_R ESET 1 EN_INTERNAL_ERR When this bit is 0, only a BAR conflict, which occurs when two BARs match the same LPC I/O address, will cause LPC_INTERNAL_ERR to be set. When this bit is 1, internal bus errors will also cause LPC_INTERNAL_ERR to be set. R/WC 0h VCC1_R ESET 0 LPC_INTERNAL_ERR This bit is set whenever a BAR conflict or an internal bus error occurs as a result of an LPC access. Once set, it remains set until cleared by being written with a 1. This signal may be used to gener- ate interrupts. See Section 5.6, "Interrupts," on page 78. R/WC 0h VCC1_R ESET Offset 0Ch Bits Description Type Default Reset Event 31:1 RESERVED RES - - 0EC_IRQ If the LPC Logical Device is selected as the source for a Serial Inter- rupt Request by an Interrupt Configuration register (see Section 5.8.4.8, "SERIRQ Interrupts," on page 87), this bit is used as the interrupt source. R/W 0h VCC1_R ESET Offset 10h Bits Description Type Default Reset Event 31:3 RESERVED RES - - 2 Handshake This bit controls throughput of LPC transactions. When this bit is a ‘0’ the part supports a 33MHz PCI Clock. When this bit is a ‘1’, the part supports a PCI Clock from 19.2MHz (includ- ing 24MHz) to 33MHz. RES 1h VCC1_ RESET Offset 08h Bits Description Type Default Reset Event |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
