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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 270 Page - Microchip Technology |
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MEC1322 датащи(HTML) 270 Page - Microchip Technology |
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270 / 456 page  MEC1322 DS00001719D-page 270 2014 - 2015 Microchip Technology Inc. 21.9.8 DMA CHANNEL N INTERRUPT STATUS 21.9.9 DMA CHANNEL N INTERRUPT ENABLE Offset 14h Bits Description Type Default Reset Event 7:3 Reserved R - - 2 STATUS_DONE This is an interrupt source register. This flags when the DMA Channel has completed a transfer suc- cessfully on its side. A completed transfer is defined as when the DMA Channel reaches its limit; Memory Start Address equals Memory End Address. A completion due to a Hardware Flow Control Terminate will not flag this interrupt. 1=Memory Start Address equals Memory End Address 0=Memory Start Address does not equal Memory End Address R/WC 0h RESET 1 STATUS_FLOW_CONTROL This is an interrupt source register. This flags when the DMA Channel has encountered a Hardware Flow Control Request after the DMA Channel has completed the transfer. This means the Master Device is attempting to overflow the DMA. 1=Hardware Flow Control is requesting after the transfer has com- pleted 0=No Hardware Flow Control event 0h RESET 0 STATUS_BUS_ERROR This is an interrupt source register. This flags when there is an Error detected over the internal 32-bit Bus. 1: Error detected. R/WC 0h RESET Offset 18h Bits Description Type Default Reset Event 7:3 Reserved R - - 2 STATUS_ENABLE_DONE This is an interrupt enable for DMA Channel Interrupt:Status Done. 1=Enable Interrupt 0=Disable Interrupt R/W 0h RESET 1 STATUS_ENABLE_FLOW_CONTROL_ERROR This is an interrupt enable for DMA Channel Interrupt:Status Flow Control Error. 1=Enable Interrupt 0=Disable Interrupt R/W 0h RESET |
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