MEC1322 datasheet(100/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 100

 2014 - 2015 Microchip Technology Inc.

6.3.1

HOST INTERFACE

The registers defined for the Chip Configuration are accessible by the Configuration Port when the device is in CONFIG

MODE. For a description of the Configuration Port and CONFIG MODE see the description of the LPC Interface.

6.4

Power, Clocks and Reset

This section defines the Power, Clock, and Reset input parameters to this block.

6.4.1

POWER DOMAINS

6.4.2

CLOCK INPUTS

This block does not require any special clock inputs.

6.4.3

RESETS

6.5

Interrupts

This block does not generate any interrupts.

6.6

Low Power Modes

This block always automatically adjusts to operate in the lowest power mode.

6.7

Description

The Chip Configuration Registers are divided into two groups: Global Configuration Registers and Logical Device Con-

figuration registers. The following descriptions assume that the LPC interface has already been configured to operate

in CONFIG MODE.

• Global Configuration Registers are always accessible via the LPC Configuration Port.

• The Logical Device Configuration registers are only accessible via the LPC Configuration Port when the corre-

sponding Logical Device Number is loaded in the Logical Device Number register. The Logical Device Number

There are 48 8-bit Global Configuration Registers (at offsets 00h through 2Fh), plus up to 208 8-bit registers associated

with each Logical Device. The Logical Device is selected with the Logical Device Number Register (Global Configuration

Sequence to Access Logical Device Configuration Register:

a) Write the number of the Logical Device being accessed in the Logical Device Number Configuration Register by

writing 07h into the INDEX PORT and the Logical Device Number into the DATA PORT.

b) Write the address of the desired logical device configuration register to the INDEX PORT and then write or read

the value of the configuration register through the DATA PORT.

Note:

Each logical device has a bank of Configuration registers that are accessible at offsets 30h to FFh via the

Configuration Port. The Logical Device number programmed in offset 07h determines which bank of con-

figuration registers is currently accessible.

TABLE 6-2:

POWER SOURCES

Name

Description

VCC1

The logic and registers implemented in this block reside on this single

power well.

TABLE 6-3:

RESET SIGNALS

Name

Description

VCC1_RESET

Power on Reset to the block. This signal resets all the register and logic

in this block to its default state.

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