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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 266 Page - Microchip Technology |
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MEC1322 датащи(HTML) 266 Page - Microchip Technology |
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266 / 456 page  MEC1322 DS00001719D-page 266 2014 - 2015 Microchip Technology Inc. 21.9.4 DMA CHANNEL N MEMORY START ADDRESS 21.9.5 DMA CHANNEL N MEMORY END ADDRESS Offset 04h Bits Description Type Default Reset Event 31:0 MEMORY_START_ADDRESS This is the starting address for the Memory device. This field is updated by Hardware after every packet transfer by the size of the transfer, as defined by DMA Channel Control:Channel Transfer Size while the DMA Channel Control:Increment Memory Address is Enabled. The Memory device is defined as the device that is the slave device in the transfer. ex. With Hardware Flow Control, the Memory device is the device that is not connected to the Hardware Flow Controlling device. Note: This field is only as large as the maximum allowed AHB Address Size in the system. If the HADDR size is 24 Bits, then Bits [31:24] will be RESERVED. R/W 0000h RESET Offset 08h Bits Description Type Default Reset Event 31:0 MEMORY_END_ADDRESS This is the ending address for the Memory device. This will define the limit of the transfer, so long as DMA Channel Control:Increment Memory Address is Enabled. When the Memory Start Address is equal to this value, the DMA will terminate the trans- fer and flag the status DMA Channel Interrupt:Status Done. Note: This field is only as large as the maximum allowed AHB Address Size in the system. If the HADDR size is 24 Bits, then Bits [31:24] will be RESERVED. R/W 0000h RESET |
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