MEC1322 datasheet(263/456 Pages) MICROCHIP

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DS00001719D-page 263

MEC1322

• The DMA Controller has 12 DMA Channels

• Each DMA Channel may be configured to communicate with any DMA capable device on the 32-bit internal

address space. Each device has been assigned a device number. See Section 21.4.3, "DMA Interface," on

page 259.

The controller will accesses SRAM buffers only with incrementing addresses (that is, it cannot start at the top of a buffer,

nor does it handle circular buffers automatically). The controller does not handle chaining (that is, automatically starting

a new DMA transfer when one finishes).

21.8.1

CONFIGURATION

The DMA Controller is enabled via the ACTIVATE bit in DMA Main Control register.

Each DMA Channel must also be individually enabled via the CHANNEL_ACTIVATE bit in the DMA Channel N Activate

to be operational.

Before starting a DMA transaction on a DMA Channel the host must assign a DMA Master to the channel via HARD-

WARE_FLOW_CONTROL_DEVICE. The host must not configure two different channels to the same DMA Master at

the same time.

Data will be transfered between the DMA Master, starting at the programmed DEVICE_ADDRESS, and the targeted

memory location, starting at the MEMORY_START_ADDRESS. The address for either the DMA Master or the targeted

memory location may remain static or it may increment. To enable the DMA Master to increment its address set the

INCREMENT_DEVICE_ADDRESS bit. To enable the targeted memory location to increment its addresses set the

INCREMENT_MEMORY_ADDRESS. The DMA transfer will continue as long as the target memory address being

accessed is less than the MEMORY_END_ADDRESS. If the DMA Controller detects that the memory location it is

attempting to access on the Target is equal to the MEMORY_END_ADDRESS it will notify the DMA Master that the

transaction is done. Otherwise the Data will be transferred in packets. The size of the packet is determined by the

TRANSFER_SIZE.

21.8.2

OPERATION

The DMA Controller is designed to move data from one memory location to another.

21.8.2.1

Establishing a Connection

A DMA Master will initiate a DMA Transaction by requesting access to a channel. The DMA arbiter, which evaluates

each channel request using a basic round robin algorithm, will grant access to the DMA master. Once granted, the chan-

nel will hold the grant until it decides to release it, by notifying the DMA Controller that it is done.

21.8.2.2

Initiating a Transfer

Once a connection is established the DMA Master will issue a DMA request to start a DMA transfer. If Firmware wants

to have a transfer request serviced it must set the RUN bit to have its transfer requests serviced.

Firmware can initiate a transaction by setting the TRANSFER_GO bit. The DMA transfer will remain active until either

the Master issues a Terminate or the DMA Controller signals that the transfer is DONE. Firmware may terminate a trans-

action by setting the TRANSFER_ABORT bit.

Data may be moved from the DMA Master to the targeted Memory address or from the targeted Memory Address to the

DMA Master. The direction of the transfer is determined by the TRANSFER_DIRECTION bit.

Once a transaction has been initiated firmware can use the STATUS_DONE bit to determine when the transaction is

completed. This status bit is routed to the interrupt interface. In the same register there are additional status bits that

indicate if the transaction completed successfully or with errors. This bits are OR’d together with the STATUS_DONE

bit to generate the interrupt event. Each status be may be individually enabled/disabled from generating this event.

Note:

If Firmware wants to prevent any other channels from being granted while it is active it can set the

LOCK_CHANNEL bit.

Note:

Before initiating a DMA transaction via firmware the hardware flow control mus be disabled via the DIS-

ABLE_HARDWARE_FLOW_CONTROL bit.

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