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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 265 Page - Microchip Technology |
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MEC1322 датащи(HTML) 265 Page - Microchip Technology |
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265 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 265 MEC1322 21.9.1 DMA MAIN CONTROL 21.9.2 DMA DATA PACKET Note 21-2 The letter ‘N’ following DMA Channel indicates the Channel Number. Each Channel implemented will have these registers to determine that channel’s operation. 21.9.3 DMA CHANNEL N ACTIVATE Offset 00h Bits Description Type Default Reset Event 7:2 Reserved R - - 1 SOFT_RESET Soft reset the entire module. This bit is self-clearing. W0b - 0 ACTIVATE Enable the blocks operation. 1=Enable block. Each individual channel must be enabled separately. 0=Disable all channels. R/WS 0b RESET Offset 04h Bits Description Type Default Reset Event 31:0 DATA_PACKET Debug register that has the data that is stored in the Data Packet. This data is read data from the currently active transfer source. R 0000h - TABLE 21-10: CHANNEL EC-ONLY REGISTER SUMMARY Offset Register Name (Mnemonic) ( Note 21-2) 00h DMA Channel N Activate 04h DMA Channel N Memory Start Address 08h DMA Channel N Memory End Address 0Ch DMA Channel N Device Address 10h DMA Channel N Control 14h DMA Channel N Interrupt Status 18h DMA Channel N Interrupt Enable Offset 00h Bits Description Type Default Reset Event 7:1 Reserved R - - 0 CHANNEL_ACTIVATE Enable this channel for operation. The DMA Main Control:Activate must also be enabled for this chan- nel to be operational. R/W 0h RESET |
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