MEC1322 datasheet(213/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 213

MEC1322

15.9.12

GIRQ19

15.9.13

GIRQ20

MCHP Reserved

[30:10]

Reserved

n/a

See Table 15-7, "GIRQx Source Register", Table 15-8,

"GIRQx Enable Set Register", Table 15-10, "GIRQx

Enable Clear Register", and Table 15-9, "GIRQx Result

and Result registers.

TABLE 15-22: BIT DEFINITIONS FOR GIRQ19 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

VCC_PWRGD

VCC_PWRGD interrupt from pin (see Note 15-2 on

page 215).

LRESET#

LRESET# interrupt from pin (see Note 15-2 on page 215).

[30:2]

Reserved

n/a

See Table 15-7, "GIRQx Source Register", Table 15-8,

"GIRQx Enable Set Register", Table 15-10, "GIRQx

Enable Clear Register", and Table 15-9, "GIRQx Result

and Result registers.

TABLE 15-23: BIT DEFINITIONS FOR GIRQ20 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

[4:0]

GPIO[204:200]

GPIO_Event

Bits[0:4] are controlled by the GPIO_Events generated by

GPIO200 through GPIO204, respectively.

The GPIO Interface can generate an interrupt source

event on a high level, low level, rising edge and falling

edge, as configured by the Interrupt Detection (int_det)

bits in the Pin Control Register associated with the GPIO

signal function.

Reserved

GPIO206

GPIO_Event

Bit 6 is controlled by the GPIO_Events generated by

GPIO206.

The GPIO Interface can generate an interrupt source

event on a high level, low level, rising edge and falling

edge, as configured by the Interrupt Detection (int_det)

bits in the Pin Control Register associated with the GPIO

signal function.

Reserved

TABLE 15-21: BIT DEFINITIONS FOR GIRQ18 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

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