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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 215 Page - Microchip Technology |
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MEC1322 датащи(HTML) 215 Page - Microchip Technology |
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215 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 215 MEC1322 Note 15-2 All wakeup interrupts associated with pins must be configured as falling edge interrupts through the associated GPIO control register. 15.9.17 BLOCK ENABLE SET REGISTER IRQ Vector Enable Set [31:0] Each IRQ Vector can be individually enabled to assert an interrupt event to the EC. 0= Writing a zero has no effect. 1 16-bit Timer_1 TIMER_32_x N This interrupt event fires when a 32-bit timer x reaches its limit. This event is sourced by the tEVENT_INTERRUPT status bit if enabled. 2 16-bit Timer_2 TIMER_32_x N This interrupt event fires when a 32-bit timer x reaches its limit. This event is sourced by the tEVENT_INTERRUPT status bit if enabled. 3 16-bit Timer_3 TIMER_32_x N This interrupt event fires when a 32-bit timer x reaches its limit. This event is sourced by the tEVENT_INTERRUPT status bit if enabled. 4 32-bit Timer_0 TIMER_32_x N This interrupt event fires when a 32-bit timer x reaches its limit. This event is sourced by the tEVENT_INTERRUPT status bit if enabled. 5 32-bit Timer_1 TIMER_32_x N This interrupt event fires when a 32-bit timer x reaches its limit. This event is sourced by the tEVENT_INTERRUPT status bit if enabled. [30:6] Reserved Reserved N Reserved 31 n/a n/a N See Table 15-7, "GIRQx Source Register", Table 15-8, "GIRQx Enable Set Register", Table 15-10, "GIRQx Enable Clear Register", and Table 15-9, "GIRQx Result Register" for a definition of this bit for the Source, Enable, and Result registers. Offset 200h 32-bit Size POWER VCC1 0000_0000h VCC1_RESET Default BIT D31 D30 D29 D28 D27 D26 D25 D24 TYPE R RRRRR R R BIT NAME Reserved BIT D23 D22 D21 D20 D19 D18 D17 D16 TYPE R/WS R/WS R/WS R/WS R/WS R/WS R/WS R/WS BIT NAME IRQ Vector Enable Set [23:16] BIT D15 D14 D13 D12 D11 D10 D9 D8 TYPE R/WS R/WS R/WS R/WS R/WS R/WS R/WS R/WS BIT NAME IRQ Vector Enable Set [15:8] BIT D7 D6D5D4D3D2 D1 D0 TYPE R RRRRR R R BIT NAME Reserved TABLE 15-26: BIT DEFINITIONS FOR GIRQ23 SOURCE, ENABLE, AND RESULT REGISTERS Bit Block Instance Name Source Name Wake Source Description |
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