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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 209 Page - Microchip Technology |
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MEC1322 датащи(HTML) 209 Page - Microchip Technology |
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209 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 209 MEC1322 15.9.6 GIRQ13 3 I2C3 / SMB3 SMB N I2C/SMBus controller 3 interrupt. This interrupt is signaled when the I2C/SMBus controller 3 asserts its interrupt request. 4 I2C0_0_WK SMB Y I2C/SMBus controller 0 (port 0) Wake interrupt. This inter- rupt is signaled when there is activity on the I2C/SMBus controller 0 port 0 data pin, I2C0_DAT0 (see Note 15-2 on page 215). 5 I2C0_1_WK SMB Y I2C/SMBus controller 0 (port 1) Wake interrupt. This inter- rupt is signaled when there is activity on the I2C/SMBus controller 0 port 1 data pin, I2C0_DAT1 (see Note 15-2 on page 215). 6 I2C2_0_WK SMB Y I2C/SMBus controller 2 (port 0) Wake interrupt. This inter- rupt is signaled when there is activity on the I2C/SMBus controller 2 (port 0) data pin, I2C2_DAT0 (see Note 15-2 on page 215). 7 I2C1_0_WK SMB Y I2C/SMBus controller 1 (port 0) Wake interrupt. This inter- rupt is signaled when there is activity on the I2C/SMBus controller 1 port 0 data pin, I2C1_DAT0 (see Note 15-2 on page 215). 8 I2C3_0_WK SMB Y I2C/SMBus controller 3 (port 0) Wake interrupt. This inter- rupt is signaled when there is activity on the I2C/SMBus controller 3 port 0 data pin, I2C3_DAT0 (see Note 15-2 on page 215). [30:9] Reserved Reserved N Reserved 31 n/a n/a N See Table 15-7, "GIRQx Source Register", Table 15-8, "GIRQx Enable Set Register", Table 15-10, "GIRQx Enable Clear Register", and Table 15-9, "GIRQx Result Register" for a definition of this bit for the Source, Enable, and Result registers. TABLE 15-16: BIT DEFINITIONS FOR GIRQ13 SOURCE, ENABLE, AND RESULT REGISTERS Bit Block Instance Name Source Name Wake Source Description [15:0] Reserved Reserved N Reserved 16 IRQ_DMA0 DMA0 N Direct Memory Access Channel 0 17 IRQ_DMA1 DMA1 N Direct Memory Access Channel 1 18 IRQ_DMA2 DMA2 N Direct Memory Access Channel 2 19 IRQ_DMA3 DMA3 N Direct Memory Access Channel 3 20 IRQ_DMA4 DMA4 N Direct Memory Access Channel 4 21 IRQ_DMA5 DMA5 N Direct Memory Access Channel 5 22 IRQ_DMA6 DMA6 N Direct Memory Access Channel 6 23 IRQ_DMA7 DMA7 N Direct Memory Access Channel 7 24 IRQ_DMA8 DMA8 N Direct Memory Access Channel 8 25 IRQ_DMA9 DMA9 N Direct Memory Access Channel 9 26 IRQ_DMA10 DMA10 N Direct Memory Access Channel 10 27 IRQ_DMA11 DMA11 N Direct Memory Access Channel 11 [30:28] Reserved Reserved N Reserved TABLE 15-15: BIT DEFINITIONS FOR GIRQ12 SOURCE, ENABLE, AND RESULT REGISTERS Bit Block Instance Name Source Name Wake Source Description |
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