MEC1322 datasheet(214/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 214

 2014 - 2015 Microchip Technology Inc.

15.9.14

GIRQ21

15.9.15

GIRQ22

15.9.16

GIRQ23

[9:8]

GPIO[211:210]

GPIO_Event

Bits[8:9] are controlled by the GPIO_Events generated by

GPIO210 through GPIO211, respectively.

The GPIO Interface can generate an interrupt source

event on a high level, low level, rising edge and falling

edge, as configured by the Interrupt Detection (int_det)

bits in the Pin Control Register associated with the GPIO

signal function.

[11:10]

MCHP Reserved

N/A

MCHP Reserved

[30:12]

Reserved

n/a

See Table 15-7, "GIRQx Source Register", Table 15-8,

"GIRQx Enable Set Register", Table 15-10, "GIRQx

Enable Clear Register", and Table 15-9, "GIRQx Result

and Result registers.

TABLE 15-24: BIT DEFINITIONS FOR GIRQ21 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

[1:0]

MCHP Reserved

n/a

[30:2]

Reserved

n/a

See Table 15-7, "GIRQx Source Register", Table 15-8,

"GIRQx Enable Set Register", Table 15-10, "GIRQx

Enable Clear Register", and Table 15-9, "GIRQx Result

and Result registers.

TABLE 15-25: BIT DEFINITIONS FOR GIRQ22 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

[30:0]

Reserved

n/a

See Table 15-7, "GIRQx Source Register", Table 15-8,

"GIRQx Enable Set Register", Table 15-10, "GIRQx

Enable Clear Register", and Table 15-9, "GIRQx Result

and Result registers.

TABLE 15-26: BIT DEFINITIONS FOR GIRQ23 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

16-bit Timer_0

TIMER_32_x

This interrupt event fires when a 32-bit timer x reaches its

limit. This event is sourced by the tEVENT_INTERRUPT

status bit if enabled.

TABLE 15-23: BIT DEFINITIONS FOR GIRQ20 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

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