MEC1322 datasheet(208/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 208

 2014 - 2015 Microchip Technology Inc.

15.9.4

GIRQ11

15.9.5

GIRQ12

TABLE 15-14: BIT DEFINITIONS FOR GIRQ11 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

[7:0]

GPIO[007:000]

GPIO_Event

Bits[0:7] are controlled by the GPIO_Events generated by

GPIO000 through GPIO007, respectively.

The GPIO Interface can generate an interrupt source

event on a high level, low level, rising edge and falling

edge, as configured by the Interrupt Detection (int_det)

bits in the Pin Control Register associated with the GPIO

signal function.

[15:8]

GPIO[017:010]

GPIO_Event

Bits[8:15] are controlled by the GPIO_Events generated

by GPIO010 through GPIO017, respectively.

The GPIO Interface can generate an interrupt source

event on a high level, low level, rising edge and falling

edge, as configured by the Interrupt Detection (int_det)

bits in the Pin Control Register associated with the GPIO

signal function.

[23:16]

GPIO[027:020]

GPIO_Event

Bits[16:23] are controlled by the GPIO_Events generated

by GPIO020 through GPIO027, respectively.

The GPIO Interface can generate an interrupt source

event on a high level, low level, rising edge and falling

edge, as configured by the Interrupt Detection (int_det)

bits in the Pin Control Register associated with the GPIO

signal function.

[30:24]

GPIO[036:030]

GPIO_Event

Bits[24:30] are controlled by the GPIO_Events generated

by GPIO030 through GPIO036, respectively.

The GPIO Interface can generate an interrupt source

event on a high level, low level, rising edge and falling

edge, as configured by the Interrupt Detection (int_det)

bits in the Pin Control Register associated with the GPIO

signal function.

n/a

See Table 15-7, "GIRQx Source Register", Table 15-8,

"GIRQx Enable Set Register", Table 15-10, "GIRQx

Enable Clear Register", and Table 15-9, "GIRQx Result

and Result registers.

TABLE 15-15: BIT DEFINITIONS FOR GIRQ12 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

I2C0 / SMB0

SMB

I2C/SMBus controller 0 interrupt. This interrupt is signaled

when the I2C/SMBus controller 0 asserts its interrupt

request.

I2C1 / SMB1

SMB

I2C/SMBus controller 1 interrupt. This interrupt is signaled

when the I2C/SMBus controller 1 asserts its interrupt

request.

I2C2 / SMB2

SMB

I2C/SMBus controller 2 interrupt. This interrupt is signaled

when the I2C/SMBus controller 2 asserts its interrupt

request.

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