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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MEC1322 датащи(PDF) 204 Page - Microchip Technology |
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MEC1322 датащи(HTML) 204 Page - Microchip Technology |
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204 / 456 page  MEC1322 DS00001719D-page 204 2014 - 2015 Microchip Technology Inc. All of the GIRQx Source, Enable, and Result registers have the same format. The following tables define the generic format for each of these registers. The bit definitions are defined in the sections that follow. The R/WC bits are sticky status bits indicating the state of interrupt source before the interrupt enable bit. GIRQ Enable Set [31:0] Each GIRQx bit can be individually enabled to assert an interrupt event. 0= Writing a zero has no effect. 1= Writing a one will enable respective GIRQx. Reading always returns the current value of the GIRQx ENABLE bit. The state of the GIRQx ENABLE bit is determined by the corresponding GIRQx Enable Set bit and the GIRQx Enable Clear bit. (0=disabled, 1-enabled) 12Ch GIRQ23 Source Register 130h GIRQ23 Enable Set Register 134h GIRQ23 Result Register 138h GIRQ23 Enable Clear Register 200h Block Enable Set Register 204h Block Enable Clear Register 208h Block IRQ Vector Register Note: The behavior of the enable bit controlled by the GIRQx Enable Set and GIRQx Enable Clear Registers, the GIRQx Source bit, and the GIRQx Result bit are illustrated in Section 15.8.1, "WAKE Generation," on page 194. TABLE 15-7: GIRQX SOURCE REGISTER Offset - 32-bit Size Power VCC1 0000_0000h VCC1_RESET Default Bit D31 D30 D29 • • • D2 D1 D0 Type R R/WC except for reserved bits, which are R Bit Name Reserved See Tables in the following subsections TABLE 15-8: GIRQX ENABLE SET REGISTER Offset - 32-bit Size POWER VCC1 0000_0000h VCC1_RESET Default BIT D31 D30 D29 • • • D2 D1 D0 TYPE R R/WS except for reserved bits, which are R BIT NAME Reserved See Tables in the following subsections TABLE 15-6: EC-ONLY REGISTER SUMMARY (CONTINUED) Offset Register Name |
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