RF64 datasheet(61/76 Pages) ETC2

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ADVANCED COMMUNICATIONS & SENSING

Page 61 of 76

RF64

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Tx_irq_1

r/w

IRQ_1 source in Tx mode:

If Data_mode(1:0) = 00 (Continuous mode):

x =>DCLK

If Data_mode(1:0) = 01 (Buffered mode) or 1x (Packet mode):

0 => Fifofull (d)

1 => Tx_done

Fifofull

Fifofull IRQ source

Goes high when FIFO is full.

/Fifoempty

/Fifoempty IRQ source

Goes low when FIFO is empty

Fifo_fill_method

r/w

FIFO filling method (Buffered mode only):

0 =>Automatically starts when a sync word is detected (d)

1 =>Manually controlled by Fifo_fill

Fifo_fill

r/w/

FIFO filling status/control (Buffered mode only):



If Fifo_fill_method = „0‟: (d)

Goes high when FIFO is being filled (sync word has been detected)

riting „1‟ clears the bit and waits for a new sync word (if Fifo_overrun_clr=0)



If Fifo_fill_method = „1‟:

0 =>Stop filling the FIFO

1 =>Start filling the FIFO

Tx_done

Tx_done IRQ source

Goes high when the last bit has left the shift register.

Fifo_overrun_clr

r/w/

Goes high when an overrun error occurred.

Writing a 1 anytime clears flag (if set) and launches a new Rx or Tx process

Res

r/w

(d): “0”, should be set to “1”.

Note:

“0” disables the RSSI IRQ source. It can be left enabled at any time, and

the user can choose to map this interrupt to IRQ0/IRQ1 or not.

RSSI_irq

r/w/

RSSI IRQ source:

Goes high when a signal above RSSI_irq_thresh is detected

riting „1‟ clears the bit

PLL_locked

r/w/

PLL status:

0 =>not locked

1 =>locked

Writing a „1‟ clears the bit

PLL_lock_en

r/w

PLL_lock detect flag mapped to pin 23:

0 => Lock detect disabled, pin 23 is HI

1 =>Lock detect enabled(d)

RSSI_irq_thresh

7-0

RSSI threshold for interrupt (coded as RSSI)

(d): “00000000”

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