RF64 datasheet(47/76 Pages) ETC2

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ADVANCED COMMUNICATIONS & SENSING

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RF64

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5.4.5. uC Connections

RF64

IRQ_0

IRQ_1

NSS_CONFIG

NSS_DATA

SCK

MOSI

MISO

Figure 41: uC Connections in Buffered Mode

Note that depending upon the application, some uC connections may not be needed:

IRQ_0: if none of the relevant IRQ sources are used. In this case, leave floating.

IRQ_1: if none of the relevant IRQ sources are used. In this case, leave floating.

MISO: if no read register access is needed and the chip is used in Tx mode only. In this case, pull up to VDD

through a 100 k

Ω resistor.

In addition, DATA pin (unused in buffered mode) should be pulled-up to VDD through a 100 k

Ω resistor.

Please refer to Table 13 for the RF64

‟s pin configuration.

5.4.6. Buffered Mode Example

 Configure all data processing related registers listed below appropriately. In this example we assume Sync

word recognition is on and Fifo_fill_method=0.

Description

MCParam

Data_mode_x

Defines data operation mode (=>Buffered)

Fifo_size

Defines FIFO size

Fifo_thresh

Defines FIFO threshold

IRQParam

Rx_stby_irq_0

Defines IRQ_0 source in Rx & Stby modes

Rx_stby_irq_1

Defines IRQ_1 source in Rx & Stby modes

Tx_irq_1

Defines IRQ_1 source in Tx mode

Fifo_fill_method

Defines FIFO filling method

Fifo_fill

Controls FIFO filling status

Tx_start_irq_0

Defines Tx start condition and IRQ_0 source

RXParam

Sync_size

Defines Sync word size

Sync_tol

Defines the error tolerance on Sync word detection

SYNCParam

Sync_value

Defines Sync word value

Table 22: Relevant Configuration Registers in Buffered Mode (data processing related only)

Tx Mode:

 Program Tx start condition and IRQs: Start Tx when FIFO is not empty (Tx_start_irq_0=1) and IRQ_1 mapped

to Tx_done (Tx_irq_1=1)

 Go to Tx mode (and wait for Tx to be ready, see Figure 50)

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