RF64 datasheet(55/76 Pages) ETC2

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ADVANCED COMMUNICATIONS & SENSING

Page 55 of 76

RF64

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Table 23: Interrupt Mapping in Rx and Stby in Packet Mode

Rx_stby_irq_x

Stby

IRQ_0

00 (d)

Payload_ready

Write_byte

/Fifoempty

Sync or Adrs_match*

IRQ_1

00 (d)

CRC_OK

Fifofull

RSSI

Fifo_threshold

*The latter if Address filtering is enabled

IRQ_0

Tx_start_irq_0=0 (d)

Fifo_threshold

Tx_start_irq_0=1

/Fifoempty

IRQ_1

Tx_irq_1=0 (d)

Fifofull

Tx_irq_1=1

Tx_done

Table 24: Interrupt Mapping in Tx Packet Mode

5.5.8. uC Connections

RF64

IRQ_0

IRQ_1

NSS_CONFIG

NSS_DATA

SCK

MOSI

MISO

Figure 48: uC Connections in Packet Mode

Note that depending upon the application, some uC connections may not be needed:

 IRQ_0: if none of the relevant IRQ sources are used. In this case, leave floating.

 IRQ_1: if none of the relevant IRQ sources are used. In this case, leave floating.

 MISO: if no read register access is needed and the chip is used in Tx mode only. In this case, pull up to VDD

through a 100 k

Ω resistor.

In addition, DATA pin (unused in packet mode) should be pulled-up to VDD through a 100 k

Ω resistor.

Please refer to Table 13 for the RF64

‟s pin configuration.

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