RF64 datasheet(23/76 Pages) ETC2

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ADVANCED COMMUNICATIONS & SENSING

Page 23 of 76

RF64

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First d

conve

LNA

LO1

d down-

ersion

RSSI

OOK

demod

Control logic

-Pattern recogn tion

Bit

-FIFO handler

synchronizer

-SPI inter ace

-Packet handler

LO2 Rx

FSK

demod

3.4. Receiver Description

The RF64 is set to receive mode when MCParam_Chip_mode = 011.

own-

rsion

Secon

conv

IF1

Baseband, IF2 in OOK

Figure 14: Receiver Architecture

3.4.1. Architecture

The RF64 receiver employs a super-heterodyne architecture. Here, the first IF is 1/9

of the RF frequency

(approximately 100MHz). The second down-conversion down-converts the I and Q signals to base band in the

case of the FSK receiver (Zero IF) and to a low-IF (IF2) for the OOK receiver.

Second

down-conversion

LO2

First

down-conversion

IF2=0

in FSK

mode

IF1

≈100MHz

Figure 15: FSK Receiver Setting

Image

frequency

LO1 Rx

Channel

Frequencyl

Second

down-conversion

First

down-conversion

IF2<0 in

FSK mode

equal to fo

IF1

≈100MHz

LO2 Rx

Figure 16: OOK Receiver Setting

Image

frequency

LO1 Rx

Channel

Frequency

After the second down-conversion stage, the received signal is channel-select filtered and amplified to a level

adequate for demodulation. Both FSK and OOK demodulation are available. Finally, an optional Bit Synchronizer

(BitSync) is provided, to be supply a synchronous clock and data stream to a companion uC in Continuous mode,

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