RF64 datasheet(37/76 Pages) ETC2

номер детали	RF64

подробное описание детали	ADVANCED COMMUNICATIONS & SENSING

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ADVANCED COMMUNICATIONS & SENSING

Page 37 of 76

RF64

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NSS_CONFIG (In)

SCK (In)

MOSI (In)

start

A(4) A(3) A(2) A(1)

Address = A1

A(0) stop

Current value at

address A1

MISO (Out)

D(7) D(6) D(5) D(4) D(3) D(2) D(1)

D(0)

Figure 28: Read Register Sequence

Note that when reading more than one register successively, it is not compulsory to toggle NSS_CONFIG back

high between two read sequences. The bytes are alternatively considered as address and value.

5.2.1.3. SPI Data

 Write Byte (before/during Tx)

To write bytes into the FIFO the timing diagram below should be carefully followed by the uC.

NSS_DATA (In)

SCK (In)

st byte written

nd byte written

MOSI (In)

D1(7)

D1(6)

D1(5)

D1(4)

D1(3)

D1(2)

D1(1)

D1(0)

D2(7)

D2(6)

D2(5)

D2(4)

D2(3)

D2(2)

D2(1)

D2(0)

MISO (Out) HZ

Figure 29: Write Bytes Sequence (ex: 2 bytes)

Note that it is compulsory to toggle NSS_DATA back high between each byte written.

The byte is pushed into the FIFO on the rising edge of NSS_DATA

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