LXT970ATC datasheet(70/74 Pages) INTEL

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LXT970A — Dual-Speed Fast Ethernet Transceiver

Datasheet

Table 53. Interrupt Enable Register (Address 17, Hex 11)

Bit

Name

Description

Type 1

Default

17.15:4

Reserved

Write as 0; ignore on read.

R/W

N/A

17.3

MIIDRVLVL

1 = Reduced MII driver levels. Pull-down strength of the MII driver is

reduced by a factor of 10, and the pull-up strength is reduced by a factor

of 8. Reduced driver levels on the MII I/O pins are recommended for

managed multi-port applications.

0 = High-strength MII driver levels that can effectively source 50 - 60 mA.

Series termination resistors (55

Ω) are recommended on all output

signals when using this level to avoid undershoot or overshoot.

R/W

17.2

LNK

CRITERIA

1 = Enhanced link loss criteria. Link loss criteria is independent of symbol

error rate. Loss of scrambler lock for more than 1 - 2 msec will brings the

link down. Link up criteria is based on symbol error rate.

0 = Standard link criteria. Both link up and link loss are based on symbol

error rate.

R/W

17.1

INTEN

1 = Enable interrupts. Must be enabled for bit 17.0 or 19.12 to be

effective.

0 = Disable interrupts.

R/W

17.0

TINT

1 = Forces MDINT Low and sets bit 18.15 = 1. Also forces interrupt

pulse on MDIO when bit 19.12 = 1.

0 = Normal operation.

This bit is ignored unless the interrupt function is enabled (17.1 = 1).

R/W

1. R/W = Read /Write

Table 54. Interrupt Status Register (Address 18, Hex 12)

Bit

Name

Description

Type 1

Default

18.15

MINT

1 = Indicates MII interrupt pending.

0 = Indicates no MII interrupt pending. This bit is cleared by reading

N/A

18.14

XTALOK

1 = Indicates that the LXT970A is fully powered up and the on-chip clocks

are stable.

0 = Indicates that XTAL circuit is not stable.

18.13:0

Reserved

Ignore

1. RO = Read Only

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