LXT970ATC datasheet(40/74 Pages) INTEL

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LXT970A — Dual-Speed Fast Ethernet Transceiver

Datasheet

2.8.5

Additional Operating Features

2.8.6

Low-Voltage-Fault Detect

The LXT970A low-voltage fault detection function prevents transmission of invalid symbols when

VCC goes below normal operating levels. If this condition occurs, the LXT970A disables the

transmit outputs and sets 20.2 = 1. Operation is automatically restored when VCC returns to

normal. Table 26 on page 49 indicates voltage levels that detect and clear the low-voltage fault

condition.

2.8.7

Power Down Mode

The LXT970A goes into power down mode when PWRDWN is asserted. In this mode, all

functions are disabled except the MDIO. The power supply current is significantly reduced. This

mode can be used for energy-efficient applications or for redundant applications where there are

two devices and one is left as a stand-by. When the LXT970A is returned to normal operation,

configuration settings of the MDIO registers are maintained. Refer to Table 22 on page 47 for

power down specifications.

2.8.8

Software Reset

Software reset causes all state machines to be reset and the LXT970A to re-configure itself to the

settings of the hardware configuration pins (MF<4:0>, FDE, CFG0, CFG1).

The LXT970A is reset via software(0.15 = 1). This bit setting is maintained while the reset

operation is running. When the reset operation is complete, the LXT70 resets bit 0.15 = 0.

2.8.9

Hardware Reset

Hardware reset causes the LXT970A to reset all of its functions and re-configure itself based on the

hardware configuration pin settings.

The LXT970A performs a hardware reset when a Low signal is detected at the RESET pin. All

operational conditions must be met for this function to operate. VCC must be above 4.75V and

stable, and the RESET signal must be asserted for two cycles of the master input clock. The

LXT970A continues to drive an internal reset for a period of 300

µs after the RESET signal is de-

asserted to ensure that all functions start up smoothly. MII registers are not available and the MDIO

output is tri-stated during the internal reset period. Refer to Table 43 on page 62 for hardware reset

specifications.

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