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LXT970ATC датащи(PDF) 29 Page - Intel Corporation |
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LXT970ATC датащи(HTML) 29 Page - Intel Corporation |
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29 / 74 page ![]() Dual-Speed Fast Ethernet Transceiver — LXT970A Datasheet 29 2.3.3 Bias Circuit Requirements A 22.1 k Ω 1% resistor must be tied between the RBIAS input and ground. High-speed signals should be kept away from this resistor. Follow the layout recommendations given in the Design Recommendations section on page 42. 2.4 Initialization At power-up or reset, the LXT970A performs the initialization sequence shown in Figure 11. 2.4.1 Control Mode Selection Mode control selection is provided via the MDDIS pin as shown in Table 15. When pin 15 (MDDIS) is High, the LXT970A enters Manual Control Mode. When MDDIS is Low, MDIO Control Mode is enabled. 2.4.1.1 MDIO Control Mode In the MDIO Control mode, the LXT970A reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface. 2.4.1.2 Manual Control Mode In the Manual Control Mode, LXT970A disables direct write operations to the MDIO registers via the MDIO Interface. The LXT970A continuously monitors the Hardware Control Interface pins and updates the MDIO registers accordingly. 2.4.2 Link Configuration When the LXT970A is first powered on, reset, or encounters a link failure state, it must determine the line speed and operating conditions to use for the network link. The LXT970A first checks the MDIO registers (initialized via the Hardware Control Interface or MDIO Interface) for operating instructions. Both control modes allow the user to either force the LXT970A to a specific configuration or allow it to auto-negotiate the optimum configuration with its link partner. Table 15. Mode Control Settings Mode MDDIS RESET PWRDWN MDIO Control Low High Low Manual Control High High Low Reset - Low Low Power Down - - High |
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