HDMP-1012 datasheet(31/42 Pages) HP

31 / 42 page

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even frames (iFLAG=0) and odd

frames (iFLAG=1).

• If iERR=1, then ERROR=1.

• If a Fill Frame is detected, then

FLAG=0.

• If a Data Frame is detected,

then FLAG=iFLAG, and iFLAG

should alternate between 0 and

1, starting with 0 and ending

with 1; otherwise, ERROR=1.

• If a Control Frame is detected,

then FLAG automatically

alternates between 0 and 1,

starting with 0.

The even or odd feature allows a

32/40-bit wide data word to be

transmitted through the link. A

2:1 multiplexer and a 1:2 demulti-

plexer are required. FLAG is used

to synchronize the even and odd

frames. Note, both Data and

Control Frames can be

transmitted as even/odd pairs, but

only Data Frames can be detected

for out of order errors.

HDMP-1014 (Rx) Link-

Control State Machine

Operation Principle

The link-control state machine

(SMC) on the Rx chip provides a

link handshake protocol enabling

the duplex link to transition from

frequency acquisition and training

mode into data mode.

The HDMP-1012/1014 Tx/Rx link

uses an explicit frequency

acquisition mode at startup that

operates on a square-wave

training sequence. This makes it

possible to use a VCO with a very

wide tuning range yet avoid the

harmonic false lock problems

associated with other circuits of

this type.

Using the SMC, a full duplex data

channel can be implemented

without additional controller or

hardware.

The State Machine

Handshake Protocol

Figure 1d shows a simplified

block diagram of the HDMP-

1012/1014 data channel con-

figured for full duplex operation.

Two HDMP-1012/1014 chipsets

are required to perform the

handshake in parallel. There are

three states that the link must go

through to complete the link

startup process:

• State 0: Frequency Acquisition

• State 1: Waiting for Peer

• State 2: Sending Data

Each side of the link decides

which of the three states that it

should be in. The decision is

based on its own past memory

and the type of frame that it is

currently receiving from the other

side of the link.

Considering only the local port of

the link, there is a transmitter

(Tx), a receiver (Rx) and a state

machine controller (SMC). The

SMC entity, although logically

distinct, is implemented on the

same die as the Rx chip. The SMC

monitors the data frame status

indicators (ERROR, DAV, CAV,

FW) from the Rx, and is able to

force (or control) various

characteristics of the Tx and the

Rx chips. The Tx chip has the

following controllable features:

• It can be forced to send a Fill

Frame using the ED input.

• The type of Fill Frame sent can

be controlled using the FF

input.

The Rx Chip has the following

controllable features:

• It can be in Frequency

acquisition or Phase-lock/Data

reception mode depending on

the state of the FDIS input.

• It can be enabled for data

reception or set in a mode in

which data frames are ignored

depending on the ACTIVE

input.

The Rx chip can also distinguish

between various types of frames.

It can also communicate the

frame type to the SMC. The

various frame types are:

• Fill Frame 0, (FF0)

• Fill Frame 1 a/b (FF1)

• Data/Control frames (Data)

• Error frames (ERROR)

The SMC can also be reset by

either the SMCRST0* or

SMCRST1* inputs. Usually one of

these inputs is used for power-on

reset, and the other is connected

to the Tx LOCKED output.

This holds the SMC in state 0 until

the transmitter PLL has locked.

Figure 15 shows the state

diagram of the SMC. The SMC is

debounced by allowing state

transitions to be made only after

at least 2 consecutive frames give

the same indication. This prevents

single bit errors from causing

false state transitions. In addition

to this debouncing mechanism,

when two consecutive ERROR or

Resets occur, a timer is enabled

forcing the SMC into state zero

for 128 frame times. Any

transition out of this initial state

can only occur after the link has

been error-free for 128 frames.

This prevents false transitions

from being made during the bit-

slipping that occurs in the initial

frequency acquisition of both the

Tx and Rx PLLs.

HDMP-1012 датащи(PDF) 31 Page - Agilent(Hewlett-Packard)

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