HDMP-1012 datasheet(36/42 Pages) HP

36 / 42 page

608

Timing

. Since the PLL of the Tx

is designed with a very high-gain

frequency/phase detector, the

relative alignment of the internal

clock and STRBIN is very tight,

and is insensitive to temperature

and other variations. The

observed external changes are

due mainly to variations in the

buffers, which are relatively small.

For convenience, the setup and

hold times are referenced back to

the user-supplied clock, STRBIN.

The actual sampling clock is

slightly advanced relative to

STRBIN due to internal delays,

and the hold time is typically

negative.

The user has to make sure that

M20SEL, FLAGSEL, DIV0, and

DIV1 have the same setting on

both Tx and Rx. The word width

of the parallel data from the host

can be either 16 bits if M20SEL =

0, or 20 bits if M20SEL = 1. Also,

the FLAG bit can be used as an

additional bit by setting

FLAGSEL=1. In the last case, the

parallel data word width is either

17 bits or 21 bits. The local

loopback test can be enabled by

setting LOOPEN high.

Single Frame Mode

(MDFSEL=0)

A block diagram showing the

single-frame mode data interface

for both the Tx and Rx, and their

associated timing diagrams are

shown in Figure xxx.

In the Tx side, the expected

frequency of the input clock

STRBIN is the bit rate of the data

frame. In this case, the setup and

hold times are referenced to the

rising edge of STRBIN. The

internal clock is buffered to form

STRBOUT which appears with a

delay of Tstrb after STRBIN.

In the Rx side, the data frame,

flag bit, CAV*, DAV*, LINKRDY,

and ERROR appear with a delay

of td1 after the falling edge of

STRBOUT. The state machine

outputs STAT0 and STAT1 appear

with a delay of td2.

Double Frame Mode

(MDFSEL=1)

A block diagram showing the

double-frame mode data interface

for both the Tx and Rx, and their

associated timing diagrams are

shown in Figure 17. This

configuration works best if the

duty cycle of STRBIN is 50%.

In the Tx side, the expected

frequency is 1/2 of the combined

frame period. This combined

frame, D0-D19, is formed by

interlacing the two frames C0-

C19 and C20-C39 with an

external 2:1 multiplexer. The Tx

locks onto STRBIN, which has the

same frequency as the bit rate of

C0-C39, and with an internal

frequency doubler, generates the

sampling clock to latch in D0-

D19, DAV*, CAV*, and FLAG.

STRBIN is also used to toggle the

2:1 multiplexer, and is fed into

Figure 18: Tx and Rx Data Interface for Single Frame Mode (MDFSEL=0).

CONFIGURATIONS

CAV*, DAV*

PLL

D00 - D19

FLAG

STRBOUT

STRBIN

CONFIGURATIONS

CAV*, DAV*, FF

LINKRDY, ERROR

D00 - D19

FLAG

STRBOUT

STAT0, STAT1

tstrb

D00 - D19

CAV*, DAV*

FLAG

STRBOUT

STRBIN

td2

D00 - D19

FLAG

CAV*, DAV*, FF

LINKRDY, ERROR

STAT0, STAT1

STRBOUT

td1

ts = SETUP TIME

th = HOLD TIME

tstrb = STRBIN TO STRBOUT DELAY

td1 = STRBOUT TO SYNCHRONOUS OUTPUTS DELAY

td2 = STRBOUT TO STATE MACHINE OUTPUTS DELAY

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