HDMP-1012 datasheet(20/42 Pages) HP

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592

Rx I/O Definition (cont’d.)

Name

Type

Signal

ECLGND

ECL Ground: Normally 0 volts. This ground is used for the ECL pad

drivers. For best performance it is suggested that coupling of the noisy

ECLGND to the clean GND and HGND grounds be minimized.

EQEN

I-ECL

Enable Input for Cable Equalization: When asserted, this signal

activates the cable equalization amplifier on the DIN, DIN* serial

data inputs.

ERROR

O-ECL

Received Data Error: Asserted when a frame is received that does

not correspond to either a valid Data, Control, or Fill frame encoding.

When FLAGSEL is not active, the Rx chip also tests for strict

alternation of flag bits during data frames. A flag bit alternation

error will also cause an ERROR indication.

FCLK

O-ECL

Frame Clock Monitor: Leave unterminated in normal use.

FDIS

I-ECL

Frequency Detector Disable Input: When active, this input

disables the Rx PLL Frequency detector and enables a phase detector.

The Frequency detector is used during the start-up sequence to

acquire wide-band lock on Fill Frames, but must be disabled prior to

sending data patterns. This input is normally controlled by the Rx

state machine.

O-ECL

Fill Frame Status: During a given STRBOUT clock cycle, if neither

DAV, CAV, or ERROR are active, then the currently received frame

is a Fill frame. The type of fill frame received is indicated by the FF

pin. If FF is low, then FF0 has been received. If FF is high, then

either FF1a or FF1b has been received.

FLAG

O-ECL

Flag Bit: If both Tx and Rx have FLAGSEL asserted, this output

indicates the value of the transmitted flag bit, then this received bit

can be treated just like an extra data bit. If both Tx and Rx have

FLAGSEL set to low, FLAG is used to differentiate the even frame

from the odd frame in the line code.

FLAGSEL

I-ECL

Flag Bit Mode Select: When this input is high, the extra FLAG bit

output is effectively an extra transparent data bit. Otherwise, the

FLAG bit is checked for alternation during data frames. Any break in

strict alternation results in an ERROR indication to the user.

GND

Ground: Normally 0 volts. This ground is used for all the core logic

other than the output drivers.

HGND

High Speed Ground: Normally 0 volts. This ground is used to

provide clean references for the high speed DIN, DIN*, LIN, LIN*,

TCLK, TCLK* inputs.

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