HDMP-1012 datasheet(40/42 Pages) HP

40 / 42 page

612

deliver ECL swings directly into

Ω. The output impedance is

matched to 50

Ω with a VSWR of

less than 2:1 to above 2 GHz. This

output is ideal for driving the I-

H50 input through a 50

Ω cable

and a 0.1 uF coupling capacitor.

The 150

Ω shunt resistor to

ground improves internal DC bias

of the O-BLL differential output

circuit. The O-BLL driver can also

be connected directly into a high

speed 50

Ω oscilloscope. For

optimum performance, both

output should see the same

impedance. It is necessary that all

used O-BLL outputs be

terminated into 50

Ω. Figure 23

shows various methods of

interfacing O-BLL to I-H50 and

standard ECL logic.

TTL and Positive 5 V

Operation

Many applications require the I/

Os to interface to the standard

TTL logic family. Such TTL/ECL

translators are available in the

industry from various

semiconductor manufacturers.

This works well, but requires two

power supplies since the system is

supporting two different logic

families. This technique is

preferred, since it is easier to

keep a single clean ground plane.

Although G-LINK has been

designed to work with conven-

tional ECL negative supply, a

single positive supply can also be

used. This basically replaces the

traditional ground and Vee planes

with the Vcc and ground planes.

Also, the termination plane Vtt is

shifted up to +3 V. In theory,

since voltages are all relative,

there should be no difference. In

practice, however, the differences

lie in how well the Vcc plane is

bypassed to ground, since all of

the I/Os are referenced to this

plane. It is therefore necessary to

separate any TTL or CMOS Vcc to

this chip set, so that the cleanest

Vcc plane can be achieved.

Figure 22. I-H50 and O-BLL Simplified Circuit Schematic.

ZO = 50 Ω

VEE

28 mA

150

O-BLL

I-H50

HGND

0.1 µF

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