HDMP-1012 datasheet(39/42 Pages) HP

39 / 42 page

611

acceptable, but will reduce noise

margins due to extra parasitics.

Each of the O-ECL outputs has a

small trickle current which turns

on the output emitter follower

such that DC logic levels would

appear without external pull-down

terminations. This feature is

useful for testing and system

debugging.

High Speed Interface: I-H50 &

O-BLL

The simplified schematic

diagrams of I-H50 and O-BLL is

shown in Figure 22. The I-H50

input cell has internal 50

Ω

resistors built into the differential

input lines. The termination is

connected via HGND which

isolates the high speed ground

currents from the internal

grounds. The DC level for the

inputs is at 0 V. Since all of the

high speed inputs into G-LINK do

not have a DC component, it is

recommended that I-H50 inputs

be AC coupled with a 0.1

µF

capacitor. It is also recommended

that the unused differential inputs

be terminated with 50

Ω. The O-

BLL output cell is designed to

found in the data sheet under Tx

/ Rx I/O Definitions

I-ECL and O-ECL

These I/O are designed to

interface directly to ECL-100K

family. A simplified schematic

diagram of I/O cell is shown in

Figure 21. Many of the ECL

interface theories and techniques

can be found in commercial ECL

data books.

The I-ECL inputs have internal

pull down resistors, such that if

left opened, the logic level will

float low. Also, the inputs can be

tied to ground directly to yield a

logic high. These inputs can be

driven from standard ECL buffers,

using conventional termination

techniques. Series terminations at

the source can also be used.

In most cases, the unconnected I-

ECL input will suffice for a logic

low. However, some I-ECL pins

with adjacent high speed lines,

such as the TCLKSEL pin in the

Rx, may be affected by crosstalk

dependent on the trace

separations in the board layout. In

this case, all pins with logic lows

can be tied together and bypassed

to ground with a 0.1 uF capacitor.

The O-ECL can each drive a 50

Ω

line terminated with 50

Ω to Vtt

= -2 V. However, because of the

multiple outputs, driving all lines

into 50

Ω loads will cause

excessive power dissipation and

may lead to undesirable current

spikes in the power and ground

planes. Therefore, it is recom-

mended that the termination

resistor, which sets the output

bias current, be limited to 300

Ω.

To minimize reflections, it is

desirable to match the character-

istic impedance of the line to the

termination resistance. But

because of PC board limitations,

realistic values of 100

Ω trans-

mission lines are more

achievable. With 100

Ω lines, it is

recommended that the maximum

distance of the transmission lines

do not exceed 10 cm.

The preferred termination

resistors are individual surface-

mount resistors, commonly

connected to Vtt = -2 V which is

properly bypassed to ground.

Resistor packs such as SIPs are

Figure 21. I-ECL and O-ECL Simplified Circuit Schematic.

VEE

ECL

INPUT

ECL

OUTPUT

VEE

VIL = -1.9 V

VTT = -2 V

16 K

800

I-ECL

O-ECL

VBB = -1.3

45 µA

ECLGND

ZO > 100 Ω

L < 10 CM

RT = 300

VTT = -2 V

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