HDMP-1012 datasheet(19/42 Pages) HP

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591

Rx I/O Definition

Name

Type

Signal

ACTIVE

I-ECL

Chip Enable: This input is normally driven by the Rx state machine

output. The ACTIVE signal is internally retimed by STRBOUT and

presented to the user as the LINKRDY signal. This is how the Rx

state machine signals the user that the start-up sequence is complete.

BCLK

O-BLL

VCO Monitor Output: These pins provide access to the internal

BCLK*

VCO clock.

CAP0A

Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A

CAP0B

should be shorted to CAP1B. A loop filter capacitor of 0.1

µf must be

CAP1A

connected across the CAP0 and CAP1 inputs to increase the loop time

CAP1B

constant.

CAV*

O-ECL

Control Frame Available Output: This active-low output indicates

that the Rx chip data outputs are receiving Control Frames. False

CAV indications may be generated during link startup.

O-ECL

Data Outputs: 20 Bit data is received and decoded when M20SEL is

active; otherwise 16 bit data is decoded and the D16-D19 bits

are undefined.

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

DAV*

O-ECL

Data Available Output: This active-low output indicates that the

Rx chip data outputs, D0..D19, have received data frames. Data

should be latched on the rising edge of STRBOUT. Note that during

link startup, false data indications may be given. The DAV* and

LINKRDY outputs can be used together to avoid confusion during

link startup.

DIN

I-H50

Normal Serial Data Input: This is the input used when LOOPEN

DIN*

is not active. When LOOPEN is high, the loop back data inputs LIN,

LIN* are used instead. An optional cable equalizer may be enabled for

the DIN, DIN* inputs by asserting EQEN.

DIV0

I-ECL

VCO Divider Select: These two pins program the VCO divider chain

DIV1

to operate at full speed, half speed, quarter speed or one-eighth speed.

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