HT9580 datasheet(42/63 Pages) HOLTEK

42 / 63 page

HT9580

April 28, 2000

Preliminary

CPU Core

The HT9580 is a high performance pager con-

troller specifically designed for use in new gen-

eration radio pagers. It is based on the M6502

core. The 6502 Microprocessor offers complete

hardware and software capability with existing

6500 series of products as well as significant en-

hancements.

Instruction register and decoder

Instructions fetched from memory are gated

onto the internal bus. These instructions are

latched into the instruction register then de-

coded, along with timing and interrupt signals,

to generate control signals for the various regis-

ters.

Timing control unit

The timing control unit keeps track of the in-

struction cycle being monitored. The unit is set

to 0 each time an instruction fetch is executed

and is advanced at the beginning of each input

clock pulse for as many cycles as required to

complete the instruction. Each data transfer

between registers depends upon decoding the

contents of both the Instruction Register and

the Timing Control Unit. There are three major

clocks in the mC as follows:

· Phase 2 In (PHI2 (IN))

This signal is from the OSC1 input pin of

HT9580. The PHI1 (OUT) and PHI2 (OUT)

are derived from this signal.

· Phase 2 Out (PHI2 (OUT))

This signal is generated from PHI2 (IN).

PHI2 (IN) provides the system timing. There

is a slight delay from PHI2 (IN).

· Phase 1 Out (PHI1 (OUT))

Inverted PHI2 (OUT) signal. There is a slight

delay from PHIN2 (IN).

Read/write

This signal is normally in a high state indicat-

ing that the mC is reading data from the data

bus memory. In the low state the data bus has

valid data from the mC to be stored at the ad-

dressed memory location.

Parameter

Description

tcyc

Clock cycle time (min)

tad

Address delay time

tah

Address hold time

tdis

Read data in setup time

tdih

Read data in hold time

tdod

Write data out delay time

tdoh

Write data out hold time

tdenbd

DATAEN delay time

twed

WE_N delay time

tsyd

SYNC delay time

tsyh

SYNC hold time

tvd

VPB delay time

tvh

VPB hold time

tsos

SOB_N setup time

tsoh

SOB_N hold time

trds

RDY setup time

trdh

RDY hold time

tress

RES_N setup time

tresh

RES_N hold time

Timing parameter annotations

Arithmetic and logic unit

All arithmetic and logic operations take place

within the ALU including incrementing and

decrementing internal registers (except for the

program counter). The ALU has no internal

memory and is used only to perform logical and

transient numerical operations.

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