HT9580 datasheet(35/63 Pages) HOLTEK

35 / 63 page

Note: The value of 0019H-bit3 STB is set when decoder enters the standby mode and cleared when de-

coder enters the ON mode.

The value of 0006H-bit4 BF_FG is dependent on the BAF pin ststus.

The value of 0019H-bit5 OR is always changed by an out of range signal.

The value of 0019H-bit6 BL is cleared 0" by the decoder Battery low signal and set 1" when

the mC sets this bit high.

The value of 0006H-bit5 DR_FG is set 1" by the decoder Data-Ready interrupt signal and

cleared ²0² when the mC clears DR_FG.

HT9580

April 28, 2000

Preliminary

· Idle word indication

The idle word recognized by the HT9580 is a

standard POCSAG idle code-word as shown

in the following table.

Bit No.

0123456789

Bit

0111101010001001

Bit No. 16

Bit

1100000110010111

· Error indication

After error correction, any code-word contain-

ing more than 2-bit random errors or 4-bit

burst errors (option) in the address or mes-

sage code-word may be indicated from the er-

ror flag position.

· Decoder and mC interface

The HT9580 has two mC interface available.

One is the pager control address (0019H),

which controls the operation and configura-

tion of the decoder. The other is the pager

message buffer address (from 0040H to

006DH), which receives the message data of

calls in the parallel mode. The data ready

(DR_FG) and battery fail (BF_FG) interrupt

flags are in the interrupt flag register

(0006H).

Bi t 0

Bi t 1

Bi t 2

Bi t 3

Bi t 4

Bi t 5

Bi t 6

Bi t 7

RE S

Bi t 7 B i t 6 Bi t 5 Bi t 4 B i t 3 B i t 2 B i t 1B i t 0

P O C S A G D ec oder

D e c oder D at a O u t put

M e s s age B u f f er

( 46 B y t e s )

BA L

BS 1

BS 2

BS 3

RS S I

CK T .

D ebounc e

Ci r c u i t

V IL =0 . 9 V

V IH =1. 0 V

D a t a R e ady I nt er r upt

P ager S y s t e m C LK

BF _ F G

( 0006 H )

DR_ F G

( 0006 H )

Bi t 4

Bi t 5

m C( NM I )

m C P A 7

( W a k e up)

0019 H

B A F ( B a tte r y F a i l In te r r u p t)

ST B

SP I R E Q S T

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