HT9580 datasheet(17/63 Pages) HOLTEK

17 / 63 page

HT9580

April 28, 2000

Preliminary

Timer registers

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

State on

POR

0007H

TMRC

TMR1MOD

TMR1CLK TMR0CLK TMR1EDG TMR0EDG

TMR1EN

TMR0EN

0u00 0000

0008H

TMR1L

TM1D7

TM1D6

TM1D5

TM1D4

TM1D3

TM1D2

TM1D1

TM1D0

uuuu uuuu

0009H

TMR1H

TM1D15

TM1D14

TM1D13

TM1D12

TM1D11

TM1D10

TM1D9

TM1D8

uuuu uuuu

000AH

TMR0

TM0D7

TM0D6

TM0D5

TM0D4

TM0D3

TM0D2

TM0D1

TM0D0

uuuu uuuu

In addition to the watchdog timer, the HT9580

provides two timers: an 8-bit timer (timer 0) and

one 16-bit timer (timer 1). Those two timers are

controlled and configured by the register TMRC.

Both timers are programmable up-count coun-

ters whose clocks may be derived from the

X1-clock (32.768kHz, 76.8kHz or 153.6kHz). To

program the timers, TMR0, TMR1L, and

TMR1H should be written with a start value.

When the timers are enabled, they will count-up

from the start value. If the timers overflow, cor-

responding interrupts will be generated. When

the timers are disabled, the counter contents

will not be reset. To reset the counter contents,

the software should write the start value again.

Since timer1 is a 16-bit counter, it is important

to note the method of writing data to both

TMR1L and TMR1H. Writing to TMR1L only

writes the data into a low byte buffer, while writ-

ing to TMR1H will simultaneously write the

high byte data and the contents of the low byte

buffer into the Timer Counter preload register

(16-bit). Note that the Timer counter preload

write operation while writing to TMR1L does

not change the contents of the preload register.

Reading TMR1H will also latch the contents of

TMR1L into the byte buffer to avoid false timing

problem. Reading TMR1L returns the contents

of the low byte buffer. In other words, the low

byte of the timer counter cannot be read directly.

It must first read TMR1H to latch the low byte

contents of the timer counter into the buffer.

TMRC is the timer counter control register,

which defines the timer counter options. The

timer1 clock source can be selected from either

the internal clock or an external input clock by bit

TMR1MOD of the TMRC register. The

timer0/timer1 can also select its clock source by

bits TMR0CLK/TMR1CLK. TMRC as shown in

the table.

Labels (TMRC0

and TMRC1)

Bits

Function

TMR0EN,

TMR1EN

Enable/disable timer counting

(0=disable; 1=enable)

TMR0EDG,

TMR1EDG

Define the TMR0 and TMR1 active edge

(0=active on low to high; 1=active on high to low)

TMR0CLK

Select TMR0 clock source

(0=X1-clock; 1=OSC1 input clock/system clock)

TMR1CLK

Select TMR1 clock source if internal clock input is selected

(0=X1-clock; 1=OSC1 input clock/system clock)

TMR1MOD

Define the TMR1 operation mode

(0=internal clock input; 1=external clock input)

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