HT9580 datasheet(10/63 Pages) HOLTEK

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Configuration register

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

State on

POR

0000H

Config.

HALT

CLK_SEL OSC_MOD

LPM

RTC

BZ_CLK

MDUT

MGEN

0001 0000

HT9580

April 28, 2000

Preliminary

Oscillator configuration

There are two clock source input pins on the

chip, the main clock and the pager decoder in-

put clock. The main clock is generated by an RC

network. The system clock may be the OSC in-

put or the X1-clock depending on bit

²CLK_SEL². The pager decoder input clock co-

mes from two external pins, X1 and X2. The fre-

quency of the sub-clock will be double that of

the X1, X2 input clock. The OSC1 main clock

will be generated from an RC network that

needs an external resistor (see Application Cir-

cuit). The system clock may be X1-clock, DF or

RC clock. If no higher frequency (RC) is needed,

the external resistor between OSC1 and OSC2

can be removed. The system clock can be

switched by bit ²CLK_SEL².If ²CLK_SEL²=0

(POR State), the system clock will be X1-clock.

In other cases, with ²CLK_SEL²=1, the OSC in-

put clock will be the system clock. The clock

switching function will assist software pro-

grammers to change the mC system clock with-

in an adequate time if necessary. The

²OSC_MOD² bit selects the OSC input clock to

be either RC or DF. If ²OSC_MOD² is set to

²low² then the RC configuration is selected, oth-

erwise the DF application is selected. The pro-

grammer should note that the condition of

²CLK_SEL², ²HALT² and ²OSC_MOD² assures

that the system clock is working properly. It is

recommended that the OSC clock source is ei-

ther DF or RC. If DF and RC are necessary, it is

required to switch the system clock to X1-clock

before switching between DF and RC. Then

switch the system clock back to the OSC input

by using bit CLK_SEL if the switching action of

DF and RC is complete. Before enter HALT

mode, the system clock must select X1-clock.

The HT9580 will generate two RTC frequen-

cies, 1Hz and 2Hz respectively, determined by

bit RTC. If the bit is logic low, the 1Hz RTC fre-

quency will be selected, otherwise the 2Hz RTC

frequency will be selected. The RTC counter is

enabled/disabled by bit RTCEN and can be

masked or not masked as determined by the bit

RTCMSK of the interrupt control register

OS C

C ont r o l

C l o ck S e l e ct

X1- c l o c k

OS C _ M O D

OS C 1

0: R C

1: D F

HA L T

S yst e m C l o ck

CL K _ S E L

0: X 1- c l o c k

1: O S C I nput

F r equen c y

D oubl er

SS T

10- bi t R i ppl e

C ount e r

Ma i n

Cl o c k

S S T C ont r o l

X1- c l o c k

OS C

I npu t

S ub- c l oc k

X1- c l o c k

C ount e r

1H z & T i m e O u t

2H z & T i m e O ut

RT C T i m e O u t

RT C

RTC block diagram

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