HT9580 datasheet(12/63 Pages) HOLTEK

12 / 63 page

HT9580

April 28, 2000

Preliminary

The WDT 7-bit counter is programmed by bits

WS0~WS2. The division ratio for the counter is

listed in the table.

WS2

WS1

WS0

Division

Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

The other pair ²TMR0_PR0² and ²TMR0_PR1²

are used to select the prescaler ratio for timer0.

The definition is shown in the table.

TMR0_PR1 TMR0_PR0

TMR0

Prescaler

Ratio

1/4

1/8

1/16

1/32

Buzzer generator registers

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

State on

POR

0003H

BZ-L

BZL7

BZL6

BZL5

BZL4

BZL3

BZL2

BZL1

BZL0

0000 0000

0004H

BZ-H

BZH7

BZH6

BZH5

BZH4

BZH3

BZH2

BZH1

BZH0

0000 0000

The buzzer generator is composed of a 16-bit

PFD counter and a duty cycle control. The coun-

ter value is set by two registers, namely BZ-H

and BZ-L. The source for this generator may be

the system clock or the X1-clock. The buzzer

generator is enabled/disabled by the register

bit ²MGEN² in the configuration regis-

ter(0000H). When this bit is set high, the

buzzer generator is activated. There is another

bit in the configuration register(0000H) which

controls the buzzer output volume, bit

²MDUT². If the bit is logic high, the output of

the BZ will be modulated by the X1-clock. The

clock source of the buzzer is selected by bit

²BZ_CLK². When BZ_CLK=0, the clock source

is the system clock. On the other hand, when

BZ_CLK=1, the value of the selector will be the

X1-clock.

The truth table for enabling/disabling the

buzzer generator is shown in the table.

MGEN Enable the

buzzer generator

Disable the

buzzer generator

X1- c l o c k

7- bi t C ount e r

1/8

9- bi t P r e s c a l e r

8 t o 1 M U X

W S 0 ~ 2

W D T t i m e- out

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