HT9580 datasheet(25/63 Pages) HOLTEK

25 / 63 page

HT9580

April 28, 2000

Preliminary

LCD Driver Chip Selection

Application

Note

LCD-CHIP0="0"

LCD-CHIP1="0"

SEDX(EPSON) series LCD

driver at 68 family MPU appli-

cation mode.

RESET is low active

KSX(SAMSUNG) series LCD

driver at 68 family MPU appli-

cation mode.

Pin options set as 68 family

MPU application mode.

LCD-CHIP0="1"

LCD-CHIP1="0"

MC14X(MOTOROLA) series

LCD driver.

LCD-CHIP0="0"

LCD-CHIP1="1"

HD66410(HITACHI) series

LCD driver.

SEDX(EPSON) series LCD

driver at 80 family MPU

application mode.

RESET is high active

KSX(SAMSUNG) series LCD

driver at 80 family MPU appli-

cation.

Pin options set as 80 family

MPU application mode.

LCD-CHIP0="1"

LCD-CHIP1="1"

N/A

C S ( S l av e)

LC D _ C S 1 ( S l av e)

L CD_ A 0

D0 ~ D 7

L CD_ E

L C D_ RW

L CD_ CL

LC D _ C S 0 ( M as t e r )

H T 9580

D0 ~ D 7

H D 66410

CS ( M a s t e r )

Ma s t e r

Sl a v e

L C D Dr i v e r

T he appl i c a t i on c i r c ui t w hen bi t " LC D - C H I P 1" = 1 and " L C D - C H I P 0 " = 0

15~ 8

Power down operation - HALT

The HALT mode is initiated by setting the con-

figuration register bit HALT high and results in

the following ...

The system clock turns off, the low power pager

sub-clock, LCD driver, pager decoder and RTC

all keep running.

The contents of the on-chip RAM and of the reg-

ister remain unchanged.

As the WDT and the WDT prescaler depend on

software control, the WDT will continue to

count when the ²HALT² bit is set high.

All the I/O ports remain in their original status.

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