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LPC1547JBD48 датащи(PDF) 13 Page - NXP Semiconductors |
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LPC1547JBD48 датащи(HTML) 13 Page - NXP Semiconductors |
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13 / 99 page ![]() LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 1 — 19 February 2014 13 of 99 NXP Semiconductors LPC15xx 32-bit ARM Cortex-M3 microcontroller PIO0_8/ADC0_0/TDO 9 12 19 [2] I; PU IO PIO0_8 — General purpose port 0 input/output 8. In boundary scan mode: TDO (Test Data Out). A ADC0_0 — ADC0 input 0. PIO0_9/ADC1_1/TDI 12 16 24 [2] I; PU IO PIO0_9 — General purpose port 0 input/output 9. In boundary scan mode: TDI (Test Data In). A ADC1_1 — ADC1 input 1. PIO0_10/ADC1_2 15 19 28 [2] I; PU IO PIO0_10 — General purpose port 0 input/output 10. A ADC1_2 — ADC1 input 2. PIO0_11/ADC1_3 18 23 33 [2] I; PU IO PIO0_11 — General purpose port 0 input/output 11. On the LQFP64 package, this pin is assigned to CAN0_RD in ISP C_CAN mode. A ADC1_3 — ADC1 input 3. PIO0_12/DAC_OUT 19 24 35 [3] I; PU IO PIO0_12 — General purpose port 0 input/output 12. If this pin is configured as a digital input, the input voltage level must not be higher than VDDA. A DAC_OUT — DAC analog output. PIO0_13/ADC1_6 21 29 43 [2] I; PU IO PIO0_13 — General purpose port 0 input/output 13. On the LQFP64 package, this pin is assigned to U0_RXD in ISP USART mode. On the LQFP48 package, this pin is assigned to CAN0_RD in ISP C_CAN mode. A ADC1_6 — ADC1 input 6. PIO0_14/ADC1_7/ SCT1_OUT5 22 30 45 [2] I; PU IO PIO0_14 — General purpose port 0 input/output 14. On the LQFP48 package, this pin is assigned to U0_RXD in ISP USART mode. A ADC1_7 — ADC1 input 7. O SCT1_OUT5 — SCTimer1/PWM output 5. PIO0_15/ADC1_8 23 31 47 [2] I; PU IO PIO0_15 — General purpose port 0 input/output 15. On the LQFP48 package, this pin is assigned to U0_TXD in ISP USART mode. A ADC1_8 — ADC1 input 8. PIO0_16/ADC1_9 24 32 49 [2] I; PU IO PIO0_16 — General purpose port 0 input/output 16. On the LQFP48 package, this is the ISP_1 boot pin. A ADC1_9 — ADC1 input 9. PIO0_17/WAKEUP/ TRST 28 39 61 [4] I; PU IO PIO0_17 — General purpose port 0 input/output 17. In boundary scan mode: TRST (Test Reset). This pin triggers a wake-up from Deep power-down mode. For wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. Pull this pin HIGH externally while in Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. Table 3. Pin description with fixed-pin functions Symbol Reset state[1] Type Description |
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