LPC1547JBD48 datasheet(21/99 Pages) NXP

21 / 99 page

LPC15XX

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 February 2014

21 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

Functional description

8.1 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware division,

hardware single-cycle multiply, interruptible/continuable multiple load and store

instructions, automatic state save and restore for interrupts, tightly integrated interrupt

controller, and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual, which is available on the official ARM website.

8.2 Memory Protection Unit (MPU)

The LPC15xx have a Memory Protection Unit (MPU) which can be used to improve the

reliability of an embedded system by protecting critical data within the user application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to eight regions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

PIO1_12

SCT0 input mux

PIO1_13

SCT0 input mux

PIO1_15

SCT1 input mux

PIO1_16

SCT1 input mux

PIO1_18

SCT2 input mux

PIO1_19

SCT2 input mux

PIO1_21

SCT3 input mux

PIO1_22

SCT3 input mux

PIO1_26

SCTIPU input SAMPLE_IN_A3

PIO1_27

FREQMEAS

Table 5.

Pins connected to the INPUT MUX and SCT IPU

Symbol

Description

LPC1547JBD48 датащи(PDF) 21 Page - NXP Semiconductors

LPC1547JBD48 датащи(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

датащи скачать

ссылки URL