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LPC1547JBD48 датащи(PDF) 75 Page - NXP Semiconductors

номер детали LPC1547JBD48
подробное описание детали  32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and 36 kB SRAM
PDF  99 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC1547JBD48 датащи(HTML) 75 Page - NXP Semiconductors

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LPC15XX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 February 2014
75 of 99
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
12.7 USART interface
The maximum USART bit rate is 15 Mbit/s in synchronous mode master mode and
18 Mbit/s in synchronous slave mode.
Remark: USART functions can be assigned to all digital pins. The characteristics are valid
for all digital pins except the open-drain pins PIO0_22 and PIO0_23.
Table 21.
USART dynamic characteristics
Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF; input slew = 10 ns. Simulated
parameters sampled at the 50 % level of the falling or rising edge; values guaranteed by design.
Symbol
Parameter
Min
Max
Unit
USART master (in synchronous mode)
tsu(D)
data input set-up time
33
-
ns
th(D)
data input hold time
0
-
ns
tv(Q)
data output valid time
-
7
ns
th(Q)
data output hold time
2
-
ns
USART slave (in synchronous mode)
tsu(D)
data input set-up time
13
-
ns
th(D)
data input hold time
0
-
ns
tv(Q)
data output valid time
-
28
ns
th(Q)
data output hold time
12
-
ns
In master mode, Tcy(clk) = U_PCLK/BRGVAL. See the LPC15xx User manual UM10736.
Fig 38. USART timing



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