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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC1547JBD48 датащи(PDF) 73 Page - NXP Semiconductors |
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LPC1547JBD48 датащи(HTML) 73 Page - NXP Semiconductors |
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73 / 99 page  LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 1 — 19 February 2014 73 of 99 NXP Semiconductors LPC15xx 32-bit ARM Cortex-M3 microcontroller 12.6 SPI interfaces The maximum data bit rate is 17 Mbit/s in master mode and in slave mode. Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_22 and PIO0_23. Table 20. SPI dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF; input slew = 1 ns. Simulated parameters sampled at the 50 % level of the rising or falling edge; values guaranteed by design. Symbol Parameter Min Max Unit SPI master tDS data set-up time 30 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 4 ns th(Q) data output hold time 2 - ns SPI slave tDS data set-up time 6 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 29 ns th(Q) data output hold time 12 - ns Tcy(clk) = CCLK/DIVVAL with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC15xx User manual UM10736. Fig 36. SPI master timing |
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