LPC1547JBD48 datasheet(47/99 Pages) NXP

47 / 99 page

LPC15XX

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 19 February 2014

47 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.38 Clock output

The LPC15xx feature a clock output function that routes the internal oscillator outputs, the

PLL outputs, or the main clock an output pin where they can be observed directly.

8.39 Wake-up process

The LPC15xx begin operation by using the 12 MHz IRC oscillator as the clock source at

power-up and when awakened from Deep power-down mode. This mechanism allows

chip operation to resume quickly. If the application uses the system oscillator or the PLL,

software must enable these components and wait for them to stabilize. Only then can the

system use the PLL and system oscillator as a clock source.

8.40 Power control

The LPC15xx support various power control features. There are four special modes of

processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode. The CPU clock rate can also be controlled as needed by

changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider

value. This power control mechanism allows a trade-off of power versus processing speed

based on application requirements. In addition, a register is provided for shutting down the

clocks to individual on-chip peripherals. This register allows fine-tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Selected peripherals have their own clock divider which provides

additional power control.

8.40.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configures the

LPC15xx for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock and to easily set the configuration options for

Deep-sleep and power-down modes.

Remark: When using the USB, configure the LPC15xx in Default mode.

8.40.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and can generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, by memory systems and related controllers, and by

internal buses.

LPC1547JBD48 датащи(PDF) 47 Page - NXP Semiconductors

LPC1547JBD48 датащи(HTML) 47 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

датащи скачать

ссылки URL