LPC1547JBD48 datasheet(52/99 Pages) NXP

52 / 99 page

LPC15XX

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Product data sheet

Rev. 1 — 19 February 2014

52 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1]

The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2]

Maximum/minimum voltage above the maximum operating voltage (see Table 11) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3]

Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_22 and PIO0_23 and except the 3 V tolerant pin PIO0_12.

[4]

Including the voltage on outputs in 3-state mode.

[5]

VDD(IO) present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD(IO) is powered down.

[6]

Applies to 3 V tolerant pins PIO0_12.

[7]

An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[8]

If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below

VDD without affecting the hysteresis range of the comparator function.

[9]

It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[10] Dependent on package type.

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

 series resistor.

10. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following

equation:

(1)

• Tamb = ambient temperature (C),

• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)

• PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Ilatch

I/O latch-up current

(0.5V

DD(IO)) < VI < (1.5VDD(IO));

Tj < 125 C

100

Tstg

storage temperature

[10]

65

+150

C

Tj(max)

maximum junction temperature

150

C

Ptot(pack)

total power dissipation (per

package)

based on package heat

transfer, not device power

consumption

-1.5

Vesd

electrostatic discharge voltage

human body model; all pins

[11] -5

Table 9.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol

Parameter

Conditions

Min

Max

Unit

amb

th j

–







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