AM79C970A datasheet(166/219 Pages) AMD

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AMD

P R E L I M I N A R Y

166

Am79C970A

TMD0

Bit

Name

Description

31–0 TBADR

Transmit Buffer address. This

field contains the address of the

transmit buffer that is associated

with this descriptor.

TMD1

Bit

Name

Description

OWN

This bit indicates whether the

descriptor entry is owned by

the host (OWN = 0) or

the

PCnet-PCI

controller

(OWN = 1). The host sets the

OWN bit after filling the buffer

pointed to by the descriptor entry.

The

PCnet-PCI

controller

clears the OWN bit after transmit-

ting the contents of the buffer.

Both the PCnet-PCI II controller

and the host must not alter a de-

scriptor entry after it has relin-

quished ownership.

ERR

ERR is the OR of UFLO, LCOL,

LCAR, RTRY or BPE. ERR is set

by the PCnet-PCI II controller

and cleared by the host. This bit

is set in the current descriptor

when the error occurs, and there-

fore may be set in any descriptor

of a chained buffer transmission.

29 ADD_FCS/NO

Bit

functions

when

_FCS

SWSTYLE (BCR20, bits 7–0) is

set

to ONE

(ILACC style).

Otherwise bit 29 functions as

ADD_FCS.

ADD_FCS

ADD_FCS dynamically controls

the generation of FCS on a

frame by frame basis. It is valid

only if the STP bit is set. When

ADD_FCS is set, the state of

DXMTFCS

ignored

and

transmitter FCS generation is

activated. When ADD_FCS is

cleared

ZERO,

FCS

generation

controlled

DXMTFCS. When APAD_XMT

(CSR4, bit 11) is set to ONE,

the setting of ADD_FCS has no

effect.

ADD_FCS

set

the host, and is not changed

by the PCnet-PCI II controller.

This

reserved

bit

the C-LANCE (Am79C90). This

function differs from the corre-

sponding ILACC function.

NO_FCS

NO_FCS dynamically controls

the generation of FCS on a frame

by frame basis. It is valid only if

the

ENP

bit

set.

When

NO_FCS is set, the state of

DXMTFCS is ignored and trans-

mitter FCS generation is deacti-

vated. When NO_FCS is cleared

to ZERO, FCS generation is con-

trolled

DXMTFCS.

When

APAD_XMT (CSR4, bit 11) is set

to ONE, the setting of NO_FCS

has no effect. NO_FCS is set by

the host, and is not changed by

the PCnet-PCI II controller. This

is a reserved bit in the C-LANCE

(Am79C90).

This

function

identical to the corresponding

ILACC function.

28 MORE/LTINT

Bit 28 always function as MORE.

The value of MORE is written by

the PCnet-PCI II controller and is

read by the host. When LTINTEN

is cleared to ZERO (CSR5, bit

14), the PCnet-PCI II controller

will never look at the content of bit

28, write operations by the host

have no effect. When LTINTEN

is set to ONE bit 28 changes its

function to LTINT on host write

operations and on PCnet-PCI II

controller read operations.

MORE indicates that more than

one retry was needed to transmit

a frame. The value of MORE is

written by the PCnet-PCI II con-

troller. This bit has meaning only

if the ENP bit is set.

LTINT

LTINT is used to suppress inter-

rupts after successful transmis-

sion on selected frames. When

LTINT is cleared to ZERO and

ENP

set

ONE,

the

PCnet-PCI II controller will not

set TINT (CSR0, bit 9) after a

successful transmission. TINT

will only be set when the last de-

scriptor of a frame has both

LTINT and ENP set to ONE.

When LTINT is cleared to ZERO,

it will only cause the suppression

of interrupts for successful trans-

mission. TINT will always be set if

the transmission has an error.

The LTINTEN overrides the func-

tion of TOKINTD (CSR5, bit 15).

ONE

ONE indicates that exactly one

retry was needed to transmit a

frame. ONE flag is not valid when

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