AM79C970A datasheet(167/219 Pages) AMD

167 / 219 page

P R E L I M I N A R Y

AMD

167

Am79C970A

LCOL is set. The value of the

ONE

bit

written

the

PCnet-PCI II controller. This bit

has meaning only if the ENP bit

is set.

DEF

Deferred

indicates

that

the

PCnet-PCI II controller had to

defer while trying to transmit a

frame. This condition occurs if

the channel is busy when the

PCnet-PCI II controller is ready

to transmit. DEF is set by

the PCnet-PCI II controller and

cleared by the host.

STP

Start of Packet indicates that

this is the first buffer to be used

by the PCnet-PCI II controller

for this frame. It is used for data

chaining buffers. The STP bit

must be set in the first buffer of

the frame, or the PCnet-PCI II

controller will skip over the

descriptor and poll the next de-

scriptor(s) until the OWN and

STP bits are set. STP is set by

the host and is not changed by

the PCnet-PCI II controller.

ENP

End of Packet indicates that this

is the last buffer to be used by the

PCnet-PCI II controller for this

frame. It is used for data chaining

buffers. If both STP and ENP

are set, the frame fits into one

buffer and there is no data

chaining. ENP is set by the host

and is not changed by the

PCnet-PCI II controller.

BPE

Bus Parity Error is set by the

PCnet-PCI II controller when a

parity error occurred on the bus

interface during a data transfers

from the transmit buffer associ-

ated with this descriptor. The

PCnet-PCI II controller will only

set BPE when the advanced par-

ity error handling is enabled by

setting APERREN (BCR20, bit

10) to ONE. BPE is set by the

PCnet-PCI

controller

and

cleared by the host.

This bit does not exist, when the

PCnet-PCI II controller is pro-

grammed to use 16-bit software

structures

for

the

descriptor

ring entries (BCR20, bits 7–0,

SWSTYLE is cleared to ZERO).

22–16

RES

Reserved locations.

15–12 ONES

These four bits must be written

as ONEs. This field is written by

the host and unchanged by the

PCnet-PCI II controller.

11–00 BCNT

Buffer Byte Count is the usable

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length

the

buffer.

This

the

number of bytes from this buffer

that will be transmitted by the

PCnet-PCI II controller. This field

is written by the host and is not

changed by the PCnet-PCI II

controller. There are no minimum

buffer size restrictions.

TMD2

Bit

Name

Description

BUFF

Buffer

error

set

the

PCnet-PCI

controller

during transmission when the

PCnet-PCI II controller does not

find the ENP flag in the current

descriptor and does not own the

next descriptor. This can occur in

either of two ways:

1. The OWN bit of the next de-

scriptor is ZERO.

2. FIFO underflow occurred be-

fore

the PCnet-PCI II con-

troller obtained the STATUS

byte (TMD1[31:24]) of the

next descriptor. BUFF is set

by the PCnet-PCI II controller

and cleared by the host.

If a Buffer Error occurs, an Un-

derflow Error will also occur.

BUFF is not valid when LCOL or

RTRY error is set during transmit

data chaining. BUFF is set by

the PCnet-PCI II controller and

cleared by the host.

UFLO

Underflow error indicates that the

transmitter has truncated a mes-

sage because it could not read

data from memory fast enough.

UFLO indicates that the FIFO

has emptied before the end of the

frame was reached.

When DXSUFLO (CSR3, bit 6) is

cleared to ZERO, the transmitter

is turned off when an UFLO error

occurs (CSR0, TXON = 0).

When DXSUFLO is set to ONE,

the

PCnet-PCI

controller

gracefully

recovers

from

UFLO error. It scans the transmit

descriptor ring until it finds the

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