AM79C970A datasheet(125/219 Pages) AMD

125 / 219 page

P R E L I M I N A R Y

AMD

125

Am79C970A

When LRT is cleared to ZERO,

the unsquelch threshold for the

RXD circuit will be the standard

10BASE-T value of 300 mV–

520 mV peak.

In either case, the RXD circuit

post

squelch

threshold

will

be one half of the unsquelch

threshold.

This bit only has meaning when

the 10BASE-T network interface

is selected.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. Cleared by

H_RESET or S_RESET and is

unaffected

setting

the

STOP bit.

TSEL

Transmit Mode Select. TSEL

controls the levels at which the

AUI drivers rest when the AUI

transmit port is idle. When TSEL

is cleared to ZERO, DO+ and

DO– yield zero differential to op-

erate transformer coupled loads

(Ethernet 2 and 802.3). When

TSEL is set to ONE, the DO+

idles at a higher value with re-

spect to DO–, yielding a logical

HIGH state (Ethernet 1).

This bit only has meaning when

the

AUI

network

interface

is selected.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. Cleared by

H_RESET or S_RESET.

8–7PORTSEL[1:0]

Port Select bits allow for software

controlled selection of the net-

work medium.

GPSIEN (CSR124, bit 4) must be

set to ONE in addition to pro-

gramming the PORTSEL bits in

order to select the GPSI port as

the active network port.

PORTSEL settings of AUI and

10BASE-T are ignored when the

ASEL bit of BCR2 (bit 1) has

been set to ONE.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. Cleared by

H_RESET or S_RESET and is

unaffected

setting

the

STOP bit.

INTL

Internal Loopback. See the de-

scription of LOOP (CSR15, bit 2).

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

DRTY

Disable Retry. When DRTY is

set to ONE, PCnet-PCI II control-

ler

will

attempt

only

one

transmission. In this mode, the

device will not protect the first 64

bytes of frame data in the trans-

mit FIFO from being overwritten,

because automatic re-transmis-

sion will not be necessary. When

DRTY is cleared to ZERO, the

PCnet-PCI II controller will at-

tempt 16 transmissions before

signaling a retry error.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set.

FCOLL

Force Collision. This bit allows

the collision logic to be tested.

The PCnet-PCI II controller must

internal

loopback

for

FCOLL to be valid. If FCOLL is

set to ONE, a collision will be

forced during loopback transmis-

sion attempts, which will result in

a Retry Error. If FCOLL is cleared

to ZERO, the Force Collision

logic will be disabled. FCOLL is

defined after the initialization

block is read.

Table 24. Loopback Configuration

LOOP

INTL

MENDECL

Loopback Mode

Non-loopback

External Loopback

Internal Loopback Include MENDEC

Internal Loopback Exclude MENDEC

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