AM79C970A datasheet(121/219 Pages) AMD

121 / 219 page

P R E L I M I N A R Y

AMD

121

Am79C970A

abort (RTABORT, bit 12) occurs.

SINT is cleared by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

SINTE

System

Interrupt

Enable.

SINTE is set, the SINT bit will be

able to set the INTR bit.

Read/Write accessible always.

SINTE is cleared to ZERO by

H_RESET or S_RESET and is

not

affected

setting

the

STOP bit.

SLPINT

Sleep Interrupt is set by the

PCnet-PCI II controller when it

comes out of sleep mode.

When SLPINT is set,

INTA is as-

serted if the enable bit SLPINTE

is ONE. Note that the assertion of

an interrupt due to SLPINT is not

dependent on the state of the

INEA bit, since INEA is cleared

by S_RESET when entering the

sleep mode.

Read/Write accessible always.

SLPINT is cleared by the host by

writing a ONE. Writing a ZERO

has no effect. SLPINT is cleared

by H_RESET and is not affected

by S_RESET or by setting the

STOP bit.

SLPINTE

Sleep

Interrupt

Enable.

SLPINTE is set, the SLPINT bit

will be able to set the INTR bit.

Read/Write accessible always.

SLPINTE is cleared to ZERO by

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

EXDINT

Excessive Deferral Interrupt is

set by the PCnet-PCI II controller

when the transmitter has experi-

enced Excessive Deferral on a

transmit frame, where Excessive

Deferral is defined in ISO 8802-3

(IEEE/ANSI 802.3).

When EXDINT is set,

INTA is as-

serted if the enable bit EXDINTE

is ONE.

Read/Write accessible always.

EXDINT is cleared by the host by

writing a ONE. Writing a ZERO

has no effect. EXDINT is cleared

by H_RESET and is not affected

by S_RESET or by setting the

STOP bit.

EXDINTE

Excessive Deferral Interrupt En-

able. If EXDINTE is set, the EX-

DINT bit will be able to set the

INTR bit.

Read/Write accessible always.

EXDINTE is cleared to ZERO by

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

MPPLBA

Magic Packet Physical Logical

Broadcast Accept. If MPPLBA is

cleared to ZERO, the PCnet-PCI

II controller will only detect a

magic packet if the destination

address of the packet matches

the content of the physical ad-

dress

(PADR).

MPPLBA is set to ONE, the desti-

nation address of the magic

packet can be unicast, multicast

or broadcast. Note that the set-

ting of MPPLBA only effects the

address detection of the magic

packet. The magic packet data

sequence must be in all cases

the same, i.e., a 16-times repeti-

tion of the the physical address

(PADR[47:0]).

Read/Write accessible always.

MPPLBA is cleared to ZERO

by H_RESET or S_RESET and

is not affected by setting the

STOP bit.

MPINT

Magic Packet Interrupt is set by

the

PCnet-PCI

controller

when the device is in magic

packet mode and it receives a

magic packet.

When MPINT is set,

INTA is as-

serted if IENA (CSR0, bit 6) and

the enable bit MPINTE are set

to ONE.

Read/Write accessible always.

MPINT is cleared by the host by

writing a ONE. Writing a ZERO

has no effect. MPINT is cleared

by H_RESET, S_RESET or by

setting the STOP bit.

MPINTE

Magic Packet Interrupt Enable. If

MPINTE is set, the MPINT bit will

be able to set the INTR bit.

Read/Write accessible always.

MPINTE is cleared to ZERO by

H_RESET or S_RESET and is

not

affected

setting

the

STOP bit.

MPEN

Magic Packet Enable. MPEN al-

lows activation of the magic

packet mode by software. The

PCnet-PCI II controller will enter

the magic packet mode when

both MPEN and MPMODE are

set to ONE.

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