AM79C970A datasheet(128/219 Pages) AMD

128 / 219 page

AMD

P R E L I M I N A R Y

128

Am79C970A

S_RESET or by setting the

STOP bit.

CSR26: Next Receive Descriptor Address Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 NRDAL

Contains the lower 16 bits of

the

receive

descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR27: Next Receive Descriptor Address Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 NRDAU

Contains the upper 16 bits of

the

receive

descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR28: Current Receive Descriptor Address

Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 CRDAL

Contains the lower 16 bits of

the current receive descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR29: Current Receive Descriptor Address

Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 CRDAU

Contains the upper 16 bits of

the current receive descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR30: Base Address of Transmit

Descriptor Ring Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

BADXL

Contains the lower 16 bits of the

base address of the transmit

descriptor ring.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR31: Base Address of Transmit

Descriptor Ring Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 BADXU

Contains the upper 16 bits of the

base address of the transmit

descriptor ring.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

CSR32: Next Transmit Descriptor Address Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

NXDAL

Contains the lower 16 bits of

the

transmit

descriptor

address pointer.

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET or by setting the

STOP bit.

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